Self-aligned ito dbr based p-contact for small pitch micro-led

ABSTRACT

A micro-light emitting diode includes a substrate including at least a first portion of an n-type semiconductor layer, and a mesa structure on the substrate and characterized by a linear lateral dimension equal to or less than about 3 μm. The mesa structure includes a plurality of epitaxial layers, and a conductive distributed Bragg reflector (DBR) on the plurality of epitaxial layers. The conductive DBR includes a plurality of transparent conductive oxide layers and covers between about 80% and about 100% of a full lateral area of the plurality of epitaxial layers. The micro-LED also includes a dielectric layer on sidewalls of the mesa structure, a reflective metal layer on sidewalls of the dielectric layer and electrically coupled to the first portion of the n-type semiconductor layer, and a first metal electrode in direct contact with the conductive DBR.

CROSS-REFERENCE TO RELATED APPLICATION

This application is a division of U.S. Non-Provisional application Ser.No. 17/177,980, filed Feb. 17, 2021, titled “SELF-ALIGNED ITO DBR BASEDP-CONTACT FOR SMALL PITCH MICRO-LED,” which is herein incorporated byreference in its entirety for all purposes.

BACKGROUND

Light emitting diodes (LEDs) convert electrical energy into opticalenergy, and offer many benefits over other light sources, such asreduced size, improved durability, and increased efficiency. LEDs can beused as light sources in many display systems, such as televisions,computer monitors, laptop computers, tablets, smartphones, projectionsystems, and wearable electronic devices. Micro-LEDs (“μLEDs”) based onIII-V semiconductors, such as alloys of AlN, GaN, InN, AlGaInP, otherquaternary phosphide compositions, and the like, have begun to bedeveloped for various display applications due to their small size(e.g., with a linear dimension less than 100 less than 50 less than 10or less than 5 μm), high packing density (and hence higher resolution),and high brightness. For example, micro-LEDs that emit light ofdifferent colors (e.g., red, green, and blue) can be used to form thesub-pixels of a display system, such as a television or a near-eyedisplay system.

SUMMARY

This disclosure relates generally to micro-light emitting diodes(micro-LEDs). More specifically, this disclosure relates to smallmicro-LEDs including conductive distributed Bragg reflectors(DBRs)-based electrical contacts and techniques for manufacturing thesmall micro-LEDs. According to certain embodiments, a micro-LED devicemay include a substrate including at least a first portion of an n-typesemiconductor layer, and may include an array of micro-LEDs on thesubstrate and characterized by a pitch equal to or less than about 4 μm.Each micro-LED of the array of micro-LEDs may include a mesa structurethat includes a plurality of epitaxial layers, and a conductivedistributed Bragg reflector (DBR) on the plurality of epitaxial layers.The conductive DBR may include a plurality of transparent conductiveoxide layers and may cover at least 80%, at least 90%, or at least 95%of a full lateral area of the plurality of epitaxial layers. Eachmicro-LED may also include a dielectric layer on sidewalls of the mesastructure, a reflective metal layer on sidewalls of the dielectric layerand electrically coupled to the first portion of the n-typesemiconductor layer, and a first metal electrode in direct contact withthe conductive DBR.

In some embodiments of the micro-LED device, the conductive DBR mayalign with the plurality of epitaxial layers and cover the full lateralarea of the plurality of epitaxial layers in the mesa structure. Theplurality of transparent conductive oxide layers of the conductive DBRmay include a first set of indium tin oxide (ITO) layers characterizedby a first refractive index, and a second set of ITO layerscharacterized by a second refractive index and interleaved with thefirst set of ITO layers. In some embodiments, the first set of ITOlayers may include crystalline ITO, and the second set of ITO layers mayinclude porous ITO. In some embodiments, the first set of ITO layers mayinclude ITO nanorods in a first orientation, while the second set of ITOlayers may include ITO nanorods in a second orientation that isdifferent from the first orientation. In some embodiments, the firstrefractive index may be greater than about 2.0 (e.g., greater than about2.1 or 2.2) for a target wavelength, and the second refractive index maybe less than about 1.7 (e.g., less than about 1.6 or 1.5) for the targetwavelength. The large refractive index contrast may help to achieve ahigh reflectance with a small number of ITO layers. In some embodiments,a reflectance of the conductive DBR for a target wavelength may begreater than about 90%, greater than about 95%, greater than about 98%,or about 100%.

In some embodiments of the micro-LED device, the plurality of epitaxiallayers may include a second portion of the n-type semiconductor layer,an active region including one or more quantum wells configured to emitvisible light, and a p-type semiconductor layer coupled to theconductive DBR. In some embodiments, each micro-LED of the array ofmicro-LEDs may include a micro-lens on the substrate. In someembodiments, the micro-LED device may include at least one of a secondmetal electrode electrically coupled to the reflective metal layer andthe first portion of the n-type semiconductor layer, or a transparentconductive oxide layer electrically coupled to the first portion of then-type semiconductor layer or the reflective metal layer.

According to certain embodiments, a micro-LED may include a substrateincluding at least a first portion of an n-type semiconductor layer; andmay include a mesa structure on the substrate and characterized by alinear lateral dimension equal to or less than about 3 μm. The mesastructure may include a plurality of epitaxial layers, and a conductivedistributed Bragg reflector (DBR) on the plurality of epitaxial layers.The conductive DBR may include a plurality of transparent conductiveoxide layers and may cover at least about 80%, at least 90%, or about100% of a full lateral area of the plurality of epitaxial layers. Themicro-LED may also include a dielectric layer on sidewalls of the mesastructure, a reflective metal layer on sidewalls of the dielectric layerand electrically coupled to the first portion of the n-typesemiconductor layer, and a first metal electrode in direct contact withthe conductive DBR.

In some embodiments of the micro-LED, the conductive DBR may align withthe plurality of epitaxial layers and may cover the full lateral area ofthe plurality of epitaxial layers in the mesa structure. The pluralityof transparent conductive oxide layers may include a first set of indiumtin oxide (ITO) layers characterized by a first refractive index, and asecond set of ITO layers characterized by a second refractive index andinterleaved with the first set of ITO layers, where the first set of ITOlayers and the second set of ITO layers may have different porosities ordifferent nanorod orientations. In some embodiments, a reflectance ofthe conductive DBR for a target wavelength may be greater than about90%, greater than about 95%, greater than about 98%, or about 100%.

According to certain embodiments, a method may include forming a layerstack on a substrate, where the layer stack may include a plurality ofepitaxial layers and a plurality of transparent conductive oxide layersthat form a conductive distributed Bragg reflector (DBR). The method mayalso include etching the layer stack using a same etch mask layer toform an array of mesa structures in the layer stack, the array of mesastructures characterized by a pitch equal to or less than about 4 μm;forming a first dielectric layer on surfaces of the array of mesastructures and regions between mesa structures in the array of mesastructures; forming a patterned metal layer on surfaces of the firstdielectric layer; depositing a second dielectric layer on the patternedmetal layer and the first dielectric layer; and forming, in the firstdielectric layer and the second dielectric layer, at least one of afirst set of metal plugs contacting the conductive DBR, or a second setof metal plugs contacting the patterned metal layer.

In some embodiments, forming the layer stack on the substrate mayinclude growing the plurality of epitaxial layers on the substrate, anddepositing the plurality of transparent conductive oxide layers on theplurality of epitaxial layers. The plurality of epitaxial layers mayinclude an n-type semiconductor layer, an active region configured toemit visible light having a first wavelength, and a p-type semiconductorlayer. The plurality of transparent conductive oxide layers may includea first set of transparent conductive oxide layers characterized by afirst refractive index, and a second set of transparent conductive oxidelayers characterized by a second refractive index and interleaved withthe first set of transparent conductive oxide layers, where areflectance of the conductive DBR for the first wavelength may bebetween about 90% and about 100%. In some embodiments, the first set oftransparent conductive oxide layers may include a first set of indiumtin oxide (ITO) layers, the second set of transparent conductive oxidelayers may include a second set of ITO layers, and the first set of ITOlayers and the second set of ITO layers have different porosities ordifferent nanorod orientations.

In some embodiments, the method may include etching, at the regionsbetween the mesa structures, the first dielectric layer and at least aportion of the n-type semiconductor layer, where forming the patternedmetal layer on the surfaces of the first dielectric layer may includeforming the patterned metal layer on exposed surfaces of the n-typesemiconductor layer. In some embodiments, the method may include forminga transparent conductive layer on the plurality of epitaxial layers,where the transparent conductive layer may be electrically coupled to atleast one of the second set of metal plugs, the patterned metal layer,or the n-type semiconductor layer. In some embodiments, the method mayinclude forming an array of light extraction structures on the pluralityof epitaxial layers, where each of the array of light extractionstructures may correspond to a respective mesa structure of the array ofmesa structures.

This summary is neither intended to identify key or essential featuresof the claimed subject matter, nor is it intended to be used inisolation to determine the scope of the claimed subject matter. Thesubject matter should be understood by reference to appropriate portionsof the entire specification of this disclosure, any or all drawings, andeach claim. The foregoing, together with other features and examples,will be described in more detail below in the following specification,claims, and accompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

Illustrative embodiments are described in detail below with reference tothe following figures.

FIG. 1 is a simplified block diagram of an example of an artificialreality system environment including a near-eye display according tocertain embodiments.

FIG. 2 is a perspective view of an example of a near-eye display in theform of a head-mounted display (HMD) device for implementing some of theexamples disclosed herein.

FIG. 3 is a perspective view of an example of a near-eye display in theform of a pair of glasses for implementing some of the examplesdisclosed herein.

FIG. 4 illustrates an example of an optical see-through augmentedreality system including a waveguide display according to certainembodiments.

FIG. 5A illustrates an example of a near-eye display device including awaveguide display according to certain embodiments.

FIG. 5B illustrates an example of a near-eye display device including awaveguide display according to certain embodiments.

FIG. 6 illustrates an example of an image source assembly in anaugmented reality system according to certain embodiments.

FIG. 7A illustrates an example of a light emitting diode (LED) having avertical mesa structure according to certain embodiments.

FIG. 7B is a cross-sectional view of an example of an LED having aparabolic mesa structure according to certain embodiments.

FIG. 8A illustrates an example of a micro-LED with a mesa structure.

FIG. 8B illustrates a simplified energy band structure of the activeregion of the example of micro-LED shown in FIG. 8A.

FIG. 9 illustrates an example of a micro-LED including a metal layeracting as both the p-contact and a back reflector.

FIG. 10 illustrates an example of a micro-LED device including aconductive DBR structure acting as both the p-contact and a backreflector according to certain embodiments.

FIG. 11A includes an example of a conductive DBR structure includingindium tin oxide (ITO) layers having different nanorod orientationsaccording to certain embodiments.

FIG. 11B illustrates an example of a conductive DBR structure includingindium tin oxide (ITO) layers having different porosities according tocertain embodiments.

FIG. 12A illustrates the simulated reflectance of an example of aconductive DBR structure according to certain embodiments.

FIG. 12B illustrates the simulated reflectance of another example of aconductive DBR structure according to certain embodiments.

FIG. 12C illustrates the simulated reflectance of another example of aconductive DBR structure according to certain embodiments.

FIGS. 13A-13F illustrate an example of a self-aligned process forfabricating a micro-LED device including a conductive DBR structureacting as both the electrical contact and a back reflector according tocertain embodiments.

FIGS. 14A-14F illustrate an example of a self-aligned process forfabricating a micro-LED device including a conductive DBR structureacting as both the electrical contact and a back reflector according tocertain embodiments.

FIG. 15 includes a flowchart illustrating an example of a self-alignedprocess for fabricating a micro-LED device including a conductive DBRstructure acting as both the electrical contact and a back reflectoraccording to certain embodiments.

FIG. 16 includes a flowchart illustrating an example of a self-alignedprocess for fabricating a micro-LED device including a conductive DBRstructure acting as both the electrical contact and a back reflectoraccording to certain embodiments.

FIG. 17A illustrates an example of a method of die-to-wafer bonding forarrays of LEDs according to certain embodiments.

FIG. 17B illustrates an example of a method of wafer-to-wafer bondingfor arrays of LEDs according to certain embodiments.

FIGS. 18A-18D illustrates an example of a method of hybrid bonding forarrays of LEDs according to certain embodiments.

FIG. 19 illustrates an example of an LED array with secondary opticalcomponents fabricated thereon according to certain embodiments.

FIG. 20 is a simplified block diagram of an electronic system of anexample of a near-eye display according to certain embodiments.

The figures depict embodiments of the present disclosure for purposes ofillustration only. One skilled in the art will readily recognize fromthe following description that alternative embodiments of the structuresand methods illustrated may be employed without departing from theprinciples, or benefits touted, of this disclosure.

In the appended figures, similar components and/or features may have thesame reference label. Further, various components of the same type maybe distinguished by following the reference label by a dash and a secondlabel that distinguishes among the similar components. If only the firstreference label is used in the specification, the description isapplicable to any one of the similar components having the same firstreference label irrespective of the second reference label.

DETAILED DESCRIPTION

This disclosure relates generally to light emitting diodes (LEDs). Morespecifically, and without limitation, techniques disclosed herein relateto small micro-LEDs including conductive distributed Bragg reflectors(DBRs)-based electrical contacts and methods for manufacturing the smallmicro-LEDs. Various inventive embodiments are described herein,including devices, systems, engineered wafers, bonded wafer/die stacks,packages, methods, processes, materials, and the like.

In some LED structures, a reflective metal (e.g., aluminum or silver)layer may be used as both an electrical contact (e.g., p-contact orn-contact) and a back reflector for redirecting generated photonstowards a light emitting surface of the LED. The reflective metalmaterial may diffuse into semiconductor material layers at a highdiffusion rate, and thus may cause a large leakage current. To reducethe diffusion and the leakage current, a conductive barrier layer havinga low diffusion rate (e.g., a titanium and/or tungsten layer) may beformed around the reflective metal layer. A dielectric layer may beformed on the barrier layer to provide additional isolation. For an LEDarray with a small pitch, such as less than about 4 μm or less thanabout 3 μm, the linear lateral dimension of each LED may be less thanabout 3 μm, less than about 2 μm, or less than about 1.5 μm. As such,the lateral dimensions of the reflective metal layer and the barrierlayer may be very small, thus leaving very little margin for alignmenterror during the subsequent fabrication processes. For example, openingapertures in the dielectric layer on the barrier layer to form metalplugs for making electrical contacts with the reflective metal layer viathe barrier layer may reach the lithographic limit and may need veryprecise alignment, since the lateral size of the apertures may need tobe even smaller than the lateral size of the barrier layer. In addition,when the pitch of the LED array is reduced, the lateral size of thereflective metal layer may need to be reduced more in order to leavesufficient room for the barrier layer and the dielectric layer at thesidewalls of the reflective metal layer to maintain a low leakage.Reducing the size of the reflective metal layer may reduce the overallreflectivity of the back reflector, and thus may reduce the efficiencyof the LEDs.

Distribute Bragg reflectors (DBRs) may be used in some light emittingdevices, such as some LEDs (e.g., resonant cavity LEDs) andvertical-cavity surface-emitting lasers (VCSELs), to reflect lightand/or form a resonant cavity. DBRs made of dielectric materials, suchas TiO₂ and SiO₂, are generally not electrically conductive. ConductiveDBRs may be formed using epitaxially grown semiconductor layers withalternating doping densities, which generally have low refractive indexcontrast. In addition, some of these semiconductor materials may not betransparent to the emitted light due to high absorption. For large pitchlight emitting devices, a DBR made of dielectric layers can be used inconjunction with metal plugs that pass through the dielectric layers toform reflective electrical contacts. For small pitch light emittingdevices, the size of the metal plugs may reach the lithographic limit.In addition, it can be difficult to etch the high aspect ratio aperturesthrough the dielectric layers and to fill the large aspect ratioapertures with metal plugs. Furthermore, a transparent current spreadinglayer, such as an ITO layer, may need to be formed under the dielectricDBRs to improve the electrical connectivity.

According to certain embodiments, a conductive DBR made of transparentconductive material may be used as the electrical contact (e.g., thep-contact), the back reflector, and the current spreading layer. In someexamples, the conductive DBR includes layers of a same transparentconductive oxide (e.g., ITO, IZO (Indium Zinc Oxide), or AZO (AluminumZinc Oxide)), where the layers may have alternating refractive indicescaused by different porosities and/or nanorod orientations of thetransparent conductive oxide. For example, the conductive DBR mayinclude a set of crystalline ITO layers (e.g., having a first refractiveindex that can be tuned to desire value, such as about 2.2 or anotherdesired value) interleaved with a set of porous ITO layers (e.g., havinga second refractive index that can be tuned to desire value, such asabout 1.5 or another desired value). In some embodiments, the conductiveDBR may include layers of different transparent conductive oxides thathave different refractive indices. Due to the high refractive indexcontrast between adjacent layers, the conductive DBR can achieve a veryhigh reflectance (e.g., >90% or >95%, such as close to 99% or 100%)using a relatively small number of layers, and thus may have a lowoverall thickness and a low resistance.

Furthermore, because no metal p-contact reflector (e.g., a silver layer)is used, the barrier layer for the diffusive reflective metal would notbe needed. As such, the conductive DBR can have about the same lateralsize as the epitaxial layers in the mesa structure to reduce the contactresistance and increase the overall reflectance of the back reflector atthe electrical contact (e.g., the p-contact), such that almost allemitted light passing through the p-type semiconductor layer may bereflected back towards the n-type semiconductor layer and the lightemitting surface of the LED.

In addition, because the conductive DBR has about the same lateral sizeas the epitaxial layers in the mesa structure, the conductive DBR layerand the epitaxial layers can be etched in a same etching process ordifferent etching steps using a same etch mask to form the individualmesa structures. Therefore, no alignment may be needed to form theconductive DBR on the epitaxial layers in each mesa structure.

As such, for the LED structures disclosed herein, the pitch and the mesasize may not be restricted by the thickness of the barrier layer and/orthe lithographic limit associated with the fabrication of the metallayer, the barrier layer, the dielectric layer, and/or the metal plugsdescribed above. In addition, the risk of misalignments during thefabrication of the mesa structures, the reflectors, and the electricalcontacts may be eliminated. Therefore, the pitch and the mesa size ofthe LEDs may be reduced to small values and the LEDs may still bereliably fabricated. Furthermore, since the conductive DBR acts as theelectrical contact (e.g., the p-contact), the current spreading layer,and the back reflector that can cover the whole active region of themesa structure to reflect all light passing through the p-typesemiconductor layer, a high total reflectance and low resistance maystill be achieved even if the pitch and the mesa size of the micro-LEDsare reduced to small values, such as a few microns or about one micron.Thus, the micro-LED structures disclosed herein are highly scalable, andmay be well suited for small-pitch micro LEDs, such as micro-LEDs withpitches less than about 4 μm or less than about 3 μm.

The micro-LEDs described herein may be used in conjunction with varioustechnologies, such as an artificial reality system. An artificialreality system, such as a head-mounted display (HMD) or heads-up display(HUD) system, generally includes a display configured to presentartificial images that depict objects in a virtual environment. Thedisplay may present virtual objects or combine images of real objectswith virtual objects, as in virtual reality (VR), augmented reality(AR), or mixed reality (MR) applications. For example, in an AR system,a user may view both displayed images of virtual objects (e.g.,computer-generated images (CGIs)) and the surrounding environment by,for example, seeing through transparent display glasses or lenses (oftenreferred to as optical see-through) or viewing displayed images of thesurrounding environment captured by a camera (often referred to as videosee-through). In some AR systems, the artificial images may be presentedto users using an LED-based display subsystem.

As used herein, the term “light emitting diode (LED)” refers to a lightsource that includes at least an n-type semiconductor layer, a p-typesemiconductor layer, and a light emitting region (i.e., active region)between the n-type semiconductor layer and the p-type semiconductorlayer. The light emitting region may include one or more semiconductorlayers that form one or more heterostructures, such as quantum wells. Insome embodiments, the light emitting region may include multiplesemiconductor layers that form one or more multiple-quantum-wells(MQWs), each including multiple (e.g., about 2 to 6) quantum wells.

As used herein, the term “micro-LED” or “μLED” refers to an LED that hasa chip where a linear dimension of the chip is less than about 200 μm,such as less than 100 μm, less than 50 μm, less than 20 μm, less than 10μm, or smaller. For example, the linear dimension of a micro-LED may beas small as 6 μm, 5 μm, 4 μm, 2 μm, or smaller. Some micro-LEDs may havea linear dimension (e.g., length or diameter) comparable to the minoritycarrier diffusion length. However, the disclosure herein is not limitedto micro-LEDs, and may also be applied to mini-LEDs and large LEDs.

As used herein, the term “LED array precursor” refers to an LED die orwafer that does not have the opposing electrical contacts and/or theassociated driver circuitry for each LED such that a driving voltage orcurrent may be applied to the LED for the LED to emit light. Forexample, an LED array precursor may be a wafer or die with an epitaxiallayer stack that may or may not include the light emitting regions, awafer or die with mesa structures formed in the epitaxial layer stack, awafer or die with LED arrays and metal contacts formed thereon butwithout the driver circuitry, and the like. Accordingly, the LED die orwafer is a precursor to a monolithic LED array that may be formed aftersubsequent processing steps are performed, such as forming mesastructures, forming metal electrodes, bonding to electrical backplane,removing the substrate, forming light-extraction structures, or thelike.

As used herein, the term “bonding” may refer to various methods forphysically and/or electrically connecting two or more devices and/orwafers, such as adhesive bonding, metal-to-metal bonding, metal oxidebonding, wafer-to-wafer bonding, die-to-wafer bonding, hybrid bonding,soldering, under-bump metallization, and the like. For example, adhesivebonding may use a curable adhesive (e.g., an epoxy) to physically bondtwo or more devices and/or wafers through adhesion. Metal-to-metalbonding may include, for example, wire bonding or flip chip bondingusing soldering interfaces (e.g., pads or balls), conductive adhesive,or welded joints between metals. Metal oxide bonding may form a metaland oxide pattern on each surface, bond the oxide sections together, andthen bond the metal sections together to create a conductive path.Wafer-to-wafer bonding may bond two wafers (e.g., silicon wafers orother semiconductor wafers) without any intermediate layers and is basedon chemical bonds between the surfaces of the two wafers. Wafer-to-waferbonding may include wafer cleaning and other preprocessing, aligning andpre-bonding at room temperature, and annealing at elevated temperatures,such as about 250° C. or higher. Die-to-wafer bonding may use bumps onone wafer to align features of a pre-formed chip with drivers of awafer. Hybrid bonding may include, for example, wafer cleaning,high-precision alignment of contacts of one wafer with contacts ofanother wafer, dielectric bonding of dielectric materials within thewafers at room temperature, and metal bonding of the contacts byannealing at, for example, 250-300° C. or higher. As used herein, theterm “bump” may refer generically to a metal interconnect used or formedduring bonding.

In the following description, for the purposes of explanation, specificdetails are set forth in order to provide a thorough understanding ofexamples of the disclosure. However, it will be apparent that variousexamples may be practiced without these specific details. For example,devices, systems, structures, assemblies, methods, and other componentsmay be shown as components in block diagram form in order not to obscurethe examples in unnecessary detail. In other instances, well-knowndevices, processes, systems, structures, and techniques may be shownwithout necessary detail in order to avoid obscuring the examples. Thefigures and description are not intended to be restrictive. The termsand expressions that have been employed in this disclosure are used asterms of description and not of limitation, and there is no intention inthe use of such terms and expressions of excluding any equivalents ofthe features shown and described or portions thereof. The word “example”is used herein to mean “serving as an example, instance, orillustration.” Any embodiment or design described herein as “example” isnot necessarily to be construed as preferred or advantageous over otherembodiments or designs.

FIG. 1 is a simplified block diagram of an example of an artificialreality system environment 100 including a near-eye display 120 inaccordance with certain embodiments. Artificial reality systemenvironment 100 shown in FIG. 1 may include near-eye display 120, anoptional external imaging device 150, and an optional input/outputinterface 140, each of which may be coupled to an optional console 110.While FIG. 1 shows an example of artificial reality system environment100 including one near-eye display 120, one external imaging device 150,and one input/output interface 140, any number of these components maybe included in artificial reality system environment 100, or any of thecomponents may be omitted. For example, there may be multiple near-eyedisplays 120 monitored by one or more external imaging devices 150 incommunication with console 110. In some configurations, artificialreality system environment 100 may not include external imaging device150, optional input/output interface 140, and optional console 110. Inalternative configurations, different or additional components may beincluded in artificial reality system environment 100.

Near-eye display 120 may be a head-mounted display that presents contentto a user. Examples of content presented by near-eye display 120 includeone or more of images, videos, audio, or any combination thereof. Insome embodiments, audio may be presented via an external device (e.g.,speakers and/or headphones) that receives audio information fromnear-eye display 120, console 110, or both, and presents audio databased on the audio information. Near-eye display 120 may include one ormore rigid bodies, which may be rigidly or non-rigidly coupled to eachother. A rigid coupling between rigid bodies may cause the coupled rigidbodies to act as a single rigid entity. A non-rigid coupling betweenrigid bodies may allow the rigid bodies to move relative to each other.In various embodiments, near-eye display 120 may be implemented in anysuitable form-factor, including a pair of glasses. Some embodiments ofnear-eye display 120 are further described below with respect to FIGS. 2and 3 . Additionally, in various embodiments, the functionalitydescribed herein may be used in a headset that combines images of anenvironment external to near-eye display 120 and artificial realitycontent (e.g., computer-generated images). Therefore, near-eye display120 may augment images of a physical, real-world environment external tonear-eye display 120 with generated content (e.g., images, video, sound,etc.) to present an augmented reality to a user.

In various embodiments, near-eye display 120 may include one or more ofdisplay electronics 122, display optics 124, and an eye-tracking unit130. In some embodiments, near-eye display 120 may also include one ormore locators 126, one or more position sensors 128, and an inertialmeasurement unit (IMU) 132. Near-eye display 120 may omit any ofeye-tracking unit 130, locators 126, position sensors 128, and IMU 132,or include additional elements in various embodiments. Additionally, insome embodiments, near-eye display 120 may include elements combiningthe function of various elements described in conjunction with FIG. 1 .

Display electronics 122 may display or facilitate the display of imagesto the user according to data received from, for example, console 110.In various embodiments, display electronics 122 may include one or moredisplay panels, such as a liquid crystal display (LCD), an organic lightemitting diode (OLED) display, an inorganic light emitting diode (ILED)display, a micro light emitting diode (μLED) display, an active-matrixOLED display (AMOLED), a transparent OLED display (TOLED), or some otherdisplay. For example, in one implementation of near-eye display 120,display electronics 122 may include a front TOLED panel, a rear displaypanel, and an optical component (e.g., an attenuator, polarizer, ordiffractive or spectral film) between the front and rear display panels.Display electronics 122 may include pixels to emit light of apredominant color such as red, green, blue, white, or yellow. In someimplementations, display electronics 122 may display a three-dimensional(3D) image through stereoscopic effects produced by two-dimensionalpanels to create a subjective perception of image depth. For example,display electronics 122 may include a left display and a right displaypositioned in front of a user's left eye and right eye, respectively.The left and right displays may present copies of an image shiftedhorizontally relative to each other to create a stereoscopic effect(i.e., a perception of image depth by a user viewing the image).

In certain embodiments, display optics 124 may display image contentoptically (e.g., using optical waveguides and couplers) or magnify imagelight received from display electronics 122, correct optical errorsassociated with the image light, and present the corrected image lightto a user of near-eye display 120. In various embodiments, displayoptics 124 may include one or more optical elements, such as, forexample, a substrate, optical waveguides, an aperture, a Fresnel lens, aconvex lens, a concave lens, a filter, input/output couplers, or anyother suitable optical elements that may affect image light emitted fromdisplay electronics 122. Display optics 124 may include a combination ofdifferent optical elements as well as mechanical couplings to maintainrelative spacing and orientation of the optical elements in thecombination. One or more optical elements in display optics 124 may havean optical coating, such as an anti-reflective coating, a reflectivecoating, a filtering coating, or a combination of different opticalcoatings.

Magnification of the image light by display optics 124 may allow displayelectronics 122 to be physically smaller, weigh less, and consume lesspower than larger displays. Additionally, magnification may increase afield of view of the displayed content. The amount of magnification ofimage light by display optics 124 may be changed by adjusting, adding,or removing optical elements from display optics 124. In someembodiments, display optics 124 may project displayed images to one ormore image planes that may be further away from the user's eyes thannear-eye display 120.

Display optics 124 may also be designed to correct one or more types ofoptical errors, such as two-dimensional optical errors,three-dimensional optical errors, or any combination thereof.Two-dimensional errors may include optical aberrations that occur in twodimensions. Example types of two-dimensional errors may include barreldistortion, pincushion distortion, longitudinal chromatic aberration,and transverse chromatic aberration. Three-dimensional errors mayinclude optical errors that occur in three dimensions. Example types ofthree-dimensional errors may include spherical aberration, comaticaberration, field curvature, and astigmatism.

Locators 126 may be objects located in specific positions on near-eyedisplay 120 relative to one another and relative to a reference point onnear-eye display 120. In some implementations, console 110 may identifylocators 126 in images captured by external imaging device 150 todetermine the artificial reality headset's position, orientation, orboth. A locator 126 may be an LED, a corner cube reflector, a reflectivemarker, a type of light source that contrasts with an environment inwhich near-eye display 120 operates, or any combination thereof. Inembodiments where locators 126 are active components (e.g., LEDs orother types of light emitting devices), locators 126 may emit light inthe visible band (e.g., about 380 nm to 750 nm), in the infrared (IR)band (e.g., about 750 nm to 1 mm), in the ultraviolet band (e.g., about10 nm to about 380 nm), in another portion of the electromagneticspectrum, or in any combination of portions of the electromagneticspectrum.

External imaging device 150 may include one or more cameras, one or morevideo cameras, any other device capable of capturing images includingone or more of locators 126, or any combination thereof. Additionally,external imaging device 150 may include one or more filters (e.g., toincrease signal to noise ratio). External imaging device 150 may beconfigured to detect light emitted or reflected from locators 126 in afield of view of external imaging device 150. In embodiments wherelocators 126 include passive elements (e.g., retroreflectors), externalimaging device 150 may include a light source that illuminates some orall of locators 126, which may retro-reflect the light to the lightsource in external imaging device 150. Slow calibration data may becommunicated from external imaging device 150 to console 110, andexternal imaging device 150 may receive one or more calibrationparameters from console 110 to adjust one or more imaging parameters(e.g., focal length, focus, frame rate, sensor temperature, shutterspeed, aperture, etc.).

Position sensors 128 may generate one or more measurement signals inresponse to motion of near-eye display 120. Examples of position sensors128 may include accelerometers, gyroscopes, magnetometers, othermotion-detecting or error-correcting sensors, or any combinationthereof. For example, in some embodiments, position sensors 128 mayinclude multiple accelerometers to measure translational motion (e.g.,forward/back, up/down, or left/right) and multiple gyroscopes to measurerotational motion (e.g., pitch, yaw, or roll). In some embodiments,various position sensors may be oriented orthogonally to each other.

IMU 132 may be an electronic device that generates fast calibration databased on measurement signals received from one or more of positionsensors 128. Position sensors 128 may be located external to IMU 132,internal to IMU 132, or any combination thereof. Based on the one ormore measurement signals from one or more position sensors 128, IMU 132may generate fast calibration data indicating an estimated position ofnear-eye display 120 relative to an initial position of near-eye display120. For example, IMU 132 may integrate measurement signals receivedfrom accelerometers over time to estimate a velocity vector andintegrate the velocity vector over time to determine an estimatedposition of a reference point on near-eye display 120. Alternatively,IMU 132 may provide the sampled measurement signals to console 110,which may determine the fast calibration data. While the reference pointmay generally be defined as a point in space, in various embodiments,the reference point may also be defined as a point within near-eyedisplay 120 (e.g., a center of IMU 132).

Eye-tracking unit 130 may include one or more eye-tracking systems. Eyetracking may refer to determining an eye's position, includingorientation and location of the eye, relative to near-eye display 120.An eye-tracking system may include an imaging system to image one ormore eyes and may optionally include a light emitter, which may generatelight that is directed to an eye such that light reflected by the eyemay be captured by the imaging system. For example, eye-tracking unit130 may include a non-coherent or coherent light source (e.g., a laserdiode) emitting light in the visible spectrum or infrared spectrum, anda camera capturing the light reflected by the user's eye. As anotherexample, eye-tracking unit 130 may capture reflected radio waves emittedby a miniature radar unit. Eye-tracking unit 130 may use low-power lightemitters that emit light at frequencies and intensities that would notinjure the eye or cause physical discomfort. Eye-tracking unit 130 maybe arranged to increase contrast in images of an eye captured byeye-tracking unit 130 while reducing the overall power consumed byeye-tracking unit 130 (e.g., reducing power consumed by a light emitterand an imaging system included in eye-tracking unit 130). For example,in some implementations, eye-tracking unit 130 may consume less than 100milliwatts of power.

Near-eye display 120 may use the orientation of the eye to, e.g.,determine an inter-pupillary distance (IPD) of the user, determine gazedirection, introduce depth cues (e.g., blur image outside of the user'smain line of sight), collect heuristics on the user interaction in theVR media (e.g., time spent on any particular subject, object, or frameas a function of exposed stimuli), some other functions that are basedin part on the orientation of at least one of the user's eyes, or anycombination thereof. Because the orientation may be determined for botheyes of the user, eye-tracking unit 130 may be able to determine wherethe user is looking. For example, determining a direction of a user'sgaze may include determining a point of convergence based on thedetermined orientations of the user's left and right eyes. A point ofconvergence may be the point where the two foveal axes of the user'seyes intersect. The direction of the user's gaze may be the direction ofa line passing through the point of convergence and the mid-pointbetween the pupils of the user's eyes.

Input/output interface 140 may be a device that allows a user to sendaction requests to console 110. An action request may be a request toperform a particular action. For example, an action request may be tostart or to end an application or to perform a particular action withinthe application. Input/output interface 140 may include one or moreinput devices. Example input devices may include a keyboard, a mouse, agame controller, a glove, a button, a touch screen, or any othersuitable device for receiving action requests and communicating thereceived action requests to console 110. An action request received bythe input/output interface 140 may be communicated to console 110, whichmay perform an action corresponding to the requested action. In someembodiments, input/output interface 140 may provide haptic feedback tothe user in accordance with instructions received from console 110. Forexample, input/output interface 140 may provide haptic feedback when anaction request is received, or when console 110 has performed arequested action and communicates instructions to input/output interface140. In some embodiments, external imaging device 150 may be used totrack input/output interface 140, such as tracking the location orposition of a controller (which may include, for example, an IR lightsource) or a hand of the user to determine the motion of the user. Insome embodiments, near-eye display 120 may include one or more imagingdevices to track input/output interface 140, such as tracking thelocation or position of a controller or a hand of the user to determinethe motion of the user.

Console 110 may provide content to near-eye display 120 for presentationto the user in accordance with information received from one or more ofexternal imaging device 150, near-eye display 120, and input/outputinterface 140. In the example shown in FIG. 1 , console 110 may includean application store 112, a headset tracking module 114, an artificialreality engine 116, and an eye-tracking module 118. Some embodiments ofconsole 110 may include different or additional modules than thosedescribed in conjunction with FIG. 1 . Functions further described belowmay be distributed among components of console 110 in a different mannerthan is described here.

In some embodiments, console 110 may include a processor and anon-transitory computer-readable storage medium storing instructionsexecutable by the processor. The processor may include multipleprocessing units executing instructions in parallel. The non-transitorycomputer-readable storage medium may be any memory, such as a hard diskdrive, a removable memory, or a solid-state drive (e.g., flash memory ordynamic random access memory (DRAM)). In various embodiments, themodules of console 110 described in conjunction with FIG. 1 may beencoded as instructions in the non-transitory computer-readable storagemedium that, when executed by the processor, cause the processor toperform the functions further described below.

Application store 112 may store one or more applications for executionby console 110. An application may include a group of instructions that,when executed by a processor, generates content for presentation to theuser. Content generated by an application may be in response to inputsreceived from the user via movement of the user's eyes or inputsreceived from the input/output interface 140. Examples of theapplications may include gaming applications, conferencing applications,video playback application, or other suitable applications.

Headset tracking module 114 may track movements of near-eye display 120using slow calibration information from external imaging device 150. Forexample, headset tracking module 114 may determine positions of areference point of near-eye display 120 using observed locators from theslow calibration information and a model of near-eye display 120.Headset tracking module 114 may also determine positions of a referencepoint of near-eye display 120 using position information from the fastcalibration information. Additionally, in some embodiments, headsettracking module 114 may use portions of the fast calibrationinformation, the slow calibration information, or any combinationthereof, to predict a future location of near-eye display 120. Headsettracking module 114 may provide the estimated or predicted futureposition of near-eye display 120 to artificial reality engine 116.

Artificial reality engine 116 may execute applications within artificialreality system environment 100 and receive position information ofnear-eye display 120, acceleration information of near-eye display 120,velocity information of near-eye display 120, predicted future positionsof near-eye display 120, or any combination thereof from headsettracking module 114. Artificial reality engine 116 may also receiveestimated eye position and orientation information from eye-trackingmodule 118. Based on the received information, artificial reality engine116 may determine content to provide to near-eye display 120 forpresentation to the user. For example, if the received informationindicates that the user has looked to the left, artificial realityengine 116 may generate content for near-eye display 120 that mirrorsthe user's eye movement in a virtual environment. Additionally,artificial reality engine 116 may perform an action within anapplication executing on console 110 in response to an action requestreceived from input/output interface 140, and provide feedback to theuser indicating that the action has been performed. The feedback may bevisual or audible feedback via near-eye display 120 or haptic feedbackvia input/output interface 140.

Eye-tracking module 118 may receive eye-tracking data from eye-trackingunit 130 and determine the position of the user's eye based on the eyetracking data. The position of the eye may include an eye's orientation,location, or both relative to near-eye display 120 or any elementthereof. Because the eye's axes of rotation change as a function of theeye's location in its socket, determining the eye's location in itssocket may allow eye-tracking module 118 to more accurately determinethe eye's orientation.

FIG. 2 is a perspective view of an example of a near-eye display in theform of an HMD device 200 for implementing some of the examplesdisclosed herein. HMD device 200 may be a part of, e.g., a VR system, anAR system, an MR system, or any combination thereof. HMD device 200 mayinclude a body 220 and a head strap 230. FIG. 2 shows a bottom side 223,a front side 225, and a left side 227 of body 220 in the perspectiveview. Head strap 230 may have an adjustable or extendible length. Theremay be a sufficient space between body 220 and head strap 230 of HMDdevice 200 for allowing a user to mount HMD device 200 onto the user'shead. In various embodiments, HMD device 200 may include additional,fewer, or different components. For example, in some embodiments, HMDdevice 200 may include eyeglass temples and temple tips as shown in, forexample, FIG. 3 below, rather than head strap 230.

HMD device 200 may present to a user media including virtual and/oraugmented views of a physical, real-world environment withcomputer-generated elements. Examples of the media presented by HMDdevice 200 may include images (e.g., two-dimensional (2D) orthree-dimensional (3D) images), videos (e.g., 2D or 3D videos), audio,or any combination thereof. The images and videos may be presented toeach eye of the user by one or more display assemblies (not shown inFIG. 2 ) enclosed in body 220 of HMD device 200. In various embodiments,the one or more display assemblies may include a single electronicdisplay panel or multiple electronic display panels (e.g., one displaypanel for each eye of the user). Examples of the electronic displaypanel(s) may include, for example, an LCD, an OLED display, an ILEDdisplay, a μLED display, an AMOLED, a TOLED, some other display, or anycombination thereof. HMD device 200 may include two eye box regions.

In some implementations, HMD device 200 may include various sensors (notshown), such as depth sensors, motion sensors, position sensors, and eyetracking sensors. Some of these sensors may use a structured lightpattern for sensing. In some implementations, HMD device 200 may includean input/output interface for communicating with a console. In someimplementations, HMD device 200 may include a virtual reality engine(not shown) that can execute applications within HMD device 200 andreceive depth information, position information, accelerationinformation, velocity information, predicted future positions, or anycombination thereof of HMD device 200 from the various sensors. In someimplementations, the information received by the virtual reality enginemay be used for producing a signal (e.g., display instructions) to theone or more display assemblies. In some implementations, HMD device 200may include locators (not shown, such as locators 126) located in fixedpositions on body 220 relative to one another and relative to areference point. Each of the locators may emit light that is detectableby an external imaging device.

FIG. 3 is a perspective view of an example of a near-eye display 300 inthe form of a pair of glasses for implementing some of the examplesdisclosed herein. Near-eye display 300 may be a specific implementationof near-eye display 120 of FIG. 1 , and may be configured to operate asa virtual reality display, an augmented reality display, and/or a mixedreality display. Near-eye display 300 may include a frame 305 and adisplay 310. Display 310 may be configured to present content to a user.In some embodiments, display 310 may include display electronics and/ordisplay optics. For example, as described above with respect to near-eyedisplay 120 of FIG. 1 , display 310 may include an LCD display panel, anLED display panel, or an optical display panel (e.g., a waveguidedisplay assembly).

Near-eye display 300 may further include various sensors 350 a, 350 b,350 c, 350 d, and 350 e on or within frame 305. In some embodiments,sensors 350 a-350 e may include one or more depth sensors, motionsensors, position sensors, inertial sensors, or ambient light sensors.In some embodiments, sensors 350 a-350 e may include one or more imagesensors configured to generate image data representing different fieldsof views in different directions. In some embodiments, sensors 350 a-350e may be used as input devices to control or influence the displayedcontent of near-eye display 300, and/or to provide an interactiveVR/AR/MR experience to a user of near-eye display 300. In someembodiments, sensors 350 a-350 e may also be used for stereoscopicimaging.

In some embodiments, near-eye display 300 may further include one ormore illuminators 330 to project light into the physical environment.The projected light may be associated with different frequency bands(e.g., visible light, infra-red light, ultra-violet light, etc.), andmay serve various purposes. For example, illuminator(s) 330 may projectlight in a dark environment (or in an environment with low intensity ofinfra-red light, ultra-violet light, etc.) to assist sensors 350 a-350 ein capturing images of different objects within the dark environment. Insome embodiments, illuminator(s) 330 may be used to project certainlight patterns onto the objects within the environment. In someembodiments, illuminator(s) 330 may be used as locators, such aslocators 126 described above with respect to FIG. 1 .

In some embodiments, near-eye display 300 may also include ahigh-resolution camera 340. Camera 340 may capture images of thephysical environment in the field of view. The captured images may beprocessed, for example, by a virtual reality engine (e.g., artificialreality engine 116 of FIG. 1 ) to add virtual objects to the capturedimages or modify physical objects in the captured images, and theprocessed images may be displayed to the user by display 310 for AR orMR applications.

FIG. 4 illustrates an example of an optical see-through augmentedreality system 400 including a waveguide display according to certainembodiments. Augmented reality system 400 may include a projector 410and a combiner 415. Projector 410 may include a light source or imagesource 412 and projector optics 414. In some embodiments, light sourceor image source 412 may include one or more micro-LED devices describedabove. In some embodiments, image source 412 may include a plurality ofpixels that displays virtual objects, such as an LCD display panel or anLED display panel. In some embodiments, image source 412 may include alight source that generates coherent or partially coherent light. Forexample, image source 412 may include a laser diode, a vertical cavitysurface emitting laser, an LED, and/or a micro-LED described above. Insome embodiments, image source 412 may include a plurality of lightsources (e.g., an array of micro-LEDs described above), each emitting amonochromatic image light corresponding to a primary color (e.g., red,green, or blue). In some embodiments, image source 412 may include threetwo-dimensional arrays of micro-LEDs, where each two-dimensional arrayof micro-LEDs may include micro-LEDs configured to emit light of aprimary color (e.g., red, green, or blue). In some embodiments, imagesource 412 may include an optical pattern generator, such as a spatiallight modulator. Projector optics 414 may include one or more opticalcomponents that can condition the light from image source 412, such asexpanding, collimating, scanning, or projecting light from image source412 to combiner 415. The one or more optical components may include, forexample, one or more lenses, liquid lenses, mirrors, apertures, and/orgratings. For example, in some embodiments, image source 412 may includeone or more one-dimensional arrays or elongated two-dimensional arraysof micro-LEDs, and projector optics 414 may include one or moreone-dimensional scanners (e.g., micro-mirrors or prisms) configured toscan the one-dimensional arrays or elongated two-dimensional arrays ofmicro-LEDs to generate image frames. In some embodiments, projectoroptics 414 may include a liquid lens (e.g., a liquid crystal lens) witha plurality of electrodes that allows scanning of the light from imagesource 412.

Combiner 415 may include an input coupler 430 for coupling light fromprojector 410 into a substrate 420 of combiner 415. Combiner 415 maytransmit at least 50% of light in a first wavelength range and reflectat least 25% of light in a second wavelength range. For example, thefirst wavelength range may be visible light from about 400 nm to about650 nm, and the second wavelength range may be in the infrared band, forexample, from about 800 nm to about 1000 nm. Input coupler 430 mayinclude a volume holographic grating, a diffractive optical element(DOE) (e.g., a surface-relief grating), a slanted surface of substrate420, or a refractive coupler (e.g., a wedge or a prism). For example,input coupler 430 may include a reflective volume Bragg grating or atransmissive volume Bragg grating. Input coupler 430 may have a couplingefficiency of greater than 30%, 50%, 75%, 90%, or higher for visiblelight. Light coupled into substrate 420 may propagate within substrate420 through, for example, total internal reflection (TIR). Substrate 420may be in the form of a lens of a pair of eyeglasses. Substrate 420 mayhave a flat or a curved surface, and may include one or more types ofdielectric materials, such as glass, quartz, plastic, polymer,poly(methyl methacrylate) (PMMA), crystal, or ceramic. A thickness ofthe substrate may range from, for example, less than about 1 mm to about10 mm or more. Substrate 420 may be transparent to visible light.

Substrate 420 may include or may be coupled to a plurality of outputcouplers 440, each configured to extract at least a portion of the lightguided by and propagating within substrate 420 from substrate 420, anddirect extracted light 460 to an eyebox 495 where an eye 490 of the userof augmented reality system 400 may be located when augmented realitysystem 400 is in use. The plurality of output couplers 440 may replicatethe exit pupil to increase the size of eyebox 495 such that thedisplayed image is visible in a larger area. As input coupler 430,output couplers 440 may include grating couplers (e.g., volumeholographic gratings or surface-relief gratings), other diffractionoptical elements (DOEs), prisms, etc. For example, output couplers 440may include reflective volume Bragg gratings or transmissive volumeBragg gratings. Output couplers 440 may have different coupling (e.g.,diffraction) efficiencies at different locations. Substrate 420 may alsoallow light 450 from the environment in front of combiner 415 to passthrough with little or no loss. Output couplers 440 may also allow light450 to pass through with little loss. For example, in someimplementations, output couplers 440 may have a very low diffractionefficiency for light 450 such that light 450 may be refracted orotherwise pass through output couplers 440 with little loss, and thusmay have a higher intensity than extracted light 460. In someimplementations, output couplers 440 may have a high diffractionefficiency for light 450 and may diffract light 450 in certain desireddirections (i.e., diffraction angles) with little loss. As a result, theuser may be able to view combined images of the environment in front ofcombiner 415 and images of virtual objects projected by projector 410.

FIG. 5A illustrates an example of a near-eye display (NED) device 500including a waveguide display 530 according to certain embodiments. NEDdevice 500 may be an example of near-eye display 120, augmented realitysystem 400, or another type of display device. NED device 500 mayinclude a light source 510, projection optics 520, and waveguide display530. Light source 510 may include multiple panels of light emitters fordifferent colors, such as a panel of red light emitters 512, a panel ofgreen light emitters 514, and a panel of blue light emitters 516. Thered light emitters 512 are organized into an array; the green lightemitters 514 are organized into an array; and the blue light emitters516 are organized into an array. The dimensions and pitches of lightemitters in light source 510 may be small. For example, each lightemitter may have a diameter less than 2 μm (e.g., about 1.2 μm) and thepitch may be less than 2 μm (e.g., about 1.5 μm). As such, the number oflight emitters in each red light emitters 512, green light emitters 514,and blue light emitters 516 can be equal to or greater than the numberof pixels in a display image, such as 960×720, 1280×720, 1440×1080,1920×1080, 2160×1080, or 2560×1080 pixels. Thus, a display image may begenerated simultaneously by light source 510. A scanning element may notbe used in NED device 500.

Before reaching waveguide display 530, the light emitted by light source510 may be conditioned by projection optics 520, which may include alens array. Projection optics 520 may collimate or focus the lightemitted by light source 510 to waveguide display 530, which may includea coupler 532 for coupling the light emitted by light source 510 intowaveguide display 530. The light coupled into waveguide display 530 maypropagate within waveguide display 530 through, for example, totalinternal reflection as described above with respect to FIG. 4 . Coupler532 may also couple portions of the light propagating within waveguidedisplay 530 out of waveguide display 530 and towards user's eye 590.

FIG. 5B illustrates an example of a near-eye display (NED) device 550including a waveguide display 580 according to certain embodiments. Insome embodiments, NED device 550 may use a scanning mirror 570 toproject light from a light source 540 to an image field where a user'seye 590 may be located. NED device 550 may be an example of near-eyedisplay 120, augmented reality system 400, or another type of displaydevice. Light source 540 may include one or more rows or one or morecolumns of light emitters of different colors, such as multiple rows ofred light emitters 542, multiple rows of green light emitters 544, andmultiple rows of blue light emitters 546. For example, red lightemitters 542, green light emitters 544, and blue light emitters 546 mayeach include N rows, each row including, for example, 2560 lightemitters (pixels). The red light emitters 542 are organized into anarray; the green light emitters 544 are organized into an array; and theblue light emitters 546 are organized into an array. In someembodiments, light source 540 may include a single line of lightemitters for each color. In some embodiments, light source 540 mayinclude multiple columns of light emitters for each of red, green, andblue colors, where each column may include, for example, 1080 lightemitters. In some embodiments, the dimensions and/or pitches of thelight emitters in light source 540 may be relatively large (e.g., about3-5 μm) and thus light source 540 may not include sufficient lightemitters for simultaneously generating a full display image. Forexample, the number of light emitters for a single color may be fewerthan the number of pixels (e.g., 2560×1080 pixels) in a display image.The light emitted by light source 540 may be a set of collimated ordiverging beams of light.

Before reaching scanning mirror 570, the light emitted by light source540 may be conditioned by various optical devices, such as collimatinglenses or a freeform optical element 560. Freeform optical element 560may include, for example, a multi-facet prism or another light foldingelement that may direct the light emitted by light source 540 towardsscanning mirror 570, such as changing the propagation direction of thelight emitted by light source 540 by, for example, about 90° or larger.In some embodiments, freeform optical element 560 may be rotatable toscan the light. Scanning mirror 570 and/or freeform optical element 560may reflect and project the light emitted by light source 540 towaveguide display 580, which may include a coupler 582 for coupling thelight emitted by light source 540 into waveguide display 580. The lightcoupled into waveguide display 580 may propagate within waveguidedisplay 580 through, for example, total internal reflection as describedabove with respect to FIG. 4 . Coupler 582 may also couple portions ofthe light propagating within waveguide display 580 out of waveguidedisplay 580 and towards user's eye 590.

Scanning mirror 570 may include a microelectromechanical system (MEMS)mirror or any other suitable mirrors. Scanning mirror 570 may rotate toscan in one or two dimensions. As scanning mirror 570 rotates, the lightemitted by light source 540 may be directed to a different area ofwaveguide display 580 such that a full display image may be projectedonto waveguide display 580 and directed to user's eye 590 by waveguidedisplay 580 in each scanning cycle. For example, in embodiments wherelight source 540 includes light emitters for all pixels in one or morerows or columns, scanning mirror 570 may be rotated in the column or rowdirection (e.g., x or y direction) to scan an image. In embodimentswhere light source 540 includes light emitters for some but not allpixels in one or more rows or columns, scanning mirror 570 may berotated in both the row and column directions (e.g., both x and ydirections) to project a display image (e.g., using a raster-typescanning pattern).

NED device 550 may operate in predefined display periods. A displayperiod (e.g., display cycle) may refer to a duration of time in which afull image is scanned or projected. For example, a display period may bea reciprocal of the desired frame rate. In NED device 550 that includesscanning mirror 570, the display period may also be referred to as ascanning period or scanning cycle. The light generation by light source540 may be synchronized with the rotation of scanning mirror 570. Forexample, each scanning cycle may include multiple scanning steps, wherelight source 540 may generate a different light pattern in eachrespective scanning step.

In each scanning cycle, as scanning mirror 570 rotates, a display imagemay be projected onto waveguide display 580 and user's eye 590. Theactual color value and light intensity (e.g., brightness) of a givenpixel location of the display image may be an average of the light beamsof the three colors (e.g., red, green, and blue) illuminating the pixellocation during the scanning period. After completing a scanning period,scanning mirror 570 may revert back to the initial position to projectlight for the first few rows of the next display image or may rotate ina reverse direction or scan pattern to project light for the nextdisplay image, where a new set of driving signals may be fed to lightsource 540. The same process may be repeated as scanning mirror 570rotates in each scanning cycle. As such, different images may beprojected to user's eye 590 in different scanning cycles.

FIG. 6 illustrates an example of an image source assembly 610 in anear-eye display system 600 according to certain embodiments. Imagesource assembly 610 may include, for example, a display panel 640 thatmay generate display images to be projected to the user's eyes, and aprojector 650 that may project the display images generated by displaypanel 640 to a waveguide display as described above with respect toFIGS. 4-5B. Display panel 640 may include a light source 642 and adriver circuit 644 for light source 642. Light source 642 may include,for example, light source 510 or 540. Projector 650 may include, forexample, freeform optical element 560, scanning mirror 570, and/orprojection optics 520 described above. Near-eye display system 600 mayalso include a controller 620 that synchronously controls light source642 and projector 650 (e.g., scanning mirror 570). Image source assembly610 may generate and output an image light to a waveguide display (notshown in FIG. 6 ), such as waveguide display 530 or 580. As describedabove, the waveguide display may receive the image light at one or moreinput-coupling elements, and guide the received image light to one ormore output-coupling elements. The input and output coupling elementsmay include, for example, a diffraction grating, a holographic grating,a prism, or any combination thereof. The input-coupling element may bechosen such that total internal reflection occurs with the waveguidedisplay. The output-coupling element may couple portions of the totalinternally reflected image light out of the waveguide display.

As described above, light source 642 may include a plurality of lightemitters arranged in an array or a matrix. Each light emitter may emitmonochromatic light, such as red light, blue light, green light,infra-red light, and the like. While RGB colors are often discussed inthis disclosure, embodiments described herein are not limited to usingred, green, and blue as primary colors. Other colors can also be used asthe primary colors of near-eye display system 600. In some embodiments,a display panel in accordance with an embodiment may use more than threeprimary colors. Each pixel in light source 642 may include threesubpixels that include a red micro-LED, a green micro-LED, and a bluemicro-LED. A semiconductor LED generally includes an active lightemitting layer within multiple layers of semiconductor materials. Themultiple layers of semiconductor materials may include differentcompound materials or a same base material with different dopants and/ordifferent doping densities. For example, the multiple layers ofsemiconductor materials may include an n-type material layer, an activeregion that may include hetero-structures (e.g., one or more quantumwells), and a p-type material layer. The multiple layers ofsemiconductor materials may be grown on a surface of a substrate havinga certain orientation. In some embodiments, to increase light extractionefficiency, a mesa that includes at least some of the layers ofsemiconductor materials may be formed.

Controller 620 may control the image rendering operations of imagesource assembly 610, such as the operations of light source 642 and/orprojector 650. For example, controller 620 may determine instructionsfor image source assembly 610 to render one or more display images. Theinstructions may include display instructions and scanning instructions.In some embodiments, the display instructions may include an image file(e.g., a bitmap file). The display instructions may be received from,for example, a console, such as console 110 described above with respectto FIG. 1 . The scanning instructions may be used by image sourceassembly 610 to generate image light. The scanning instructions mayspecify, for example, a type of a source of image light (e.g.,monochromatic or polychromatic), a scanning rate, an orientation of ascanning apparatus, one or more illumination parameters, or anycombination thereof. Controller 620 may include a combination ofhardware, software, and/or firmware not shown here so as not to obscureother aspects of the present disclosure.

In some embodiments, controller 620 may be a graphics processing unit(GPU) of a display device. In other embodiments, controller 620 may beother kinds of processors. The operations performed by controller 620may include taking content for display and dividing the content intodiscrete sections. Controller 620 may provide to light source 642scanning instructions that include an address corresponding to anindividual source element of light source 642 and/or an electrical biasapplied to the individual source element. Controller 620 may instructlight source 642 to sequentially present the discrete sections usinglight emitters corresponding to one or more rows of pixels in an imageultimately displayed to the user. Controller 620 may also instructprojector 650 to perform different adjustments of the light. Forexample, controller 620 may control projector 650 to scan the discretesections to different areas of a coupling element of the waveguidedisplay (e.g., waveguide display 580) as described above with respect toFIG. 5B. As such, at the exit pupil of the waveguide display, eachdiscrete portion is presented in a different respective location. Whileeach discrete section is presented at a different respective time, thepresentation and scanning of the discrete sections occur fast enoughsuch that a user's eye may integrate the different sections into asingle image or series of images.

Image processor 630 may be a general-purpose processor and/or one ormore application-specific circuits that are dedicated to performing thefeatures described herein. In one embodiment, a general-purposeprocessor may be coupled to a memory to execute software instructionsthat cause the processor to perform certain processes described herein.In another embodiment, image processor 630 may be one or more circuitsthat are dedicated to performing certain features. While image processor630 in FIG. 6 is shown as a stand-alone unit that is separate fromcontroller 620 and driver circuit 644, image processor 630 may be asub-unit of controller 620 or driver circuit 644 in other embodiments.In other words, in those embodiments, controller 620 or driver circuit644 may perform various image processing functions of image processor630. Image processor 630 may also be referred to as an image processingcircuit.

In the example shown in FIG. 6 , light source 642 may be driven bydriver circuit 644, based on data or instructions (e.g., display andscanning instructions) sent from controller 620 or image processor 630.In one embodiment, driver circuit 644 may include a circuit panel thatconnects to and mechanically holds various light emitters of lightsource 642. Light source 642 may emit light in accordance with one ormore illumination parameters that are set by the controller 620 andpotentially adjusted by image processor 630 and driver circuit 644. Anillumination parameter may be used by light source 642 to generatelight. An illumination parameter may include, for example, sourcewavelength, pulse rate, pulse amplitude, beam type (continuous orpulsed), other parameter(s) that may affect the emitted light, or anycombination thereof. In some embodiments, the source light generated bylight source 642 may include multiple beams of red light, green light,and blue light, or any combination thereof.

Projector 650 may perform a set of optical functions, such as focusing,combining, conditioning, or scanning the image light generated by lightsource 642. In some embodiments, projector 650 may include a combiningassembly, a light conditioning assembly, or a scanning mirror assembly.Projector 650 may include one or more optical components that opticallyadjust and potentially re-direct the light from light source 642. Oneexample of the adjustment of light may include conditioning the light,such as expanding, collimating, correcting for one or more opticalerrors (e.g., field curvature, chromatic aberration, etc.), some otheradjustments of the light, or any combination thereof. The opticalcomponents of projector 650 may include, for example, lenses, mirrors,apertures, gratings, or any combination thereof.

Projector 650 may redirect image light via its one or more reflectiveand/or refractive portions so that the image light is projected atcertain orientations toward the waveguide display. The location wherethe image light is redirected toward the waveguide display may depend onspecific orientations of the one or more reflective and/or refractiveportions. In some embodiments, projector 650 includes a single scanningmirror that scans in at least two dimensions. In other embodiments,projector 650 may include a plurality of scanning mirrors that each scanin directions orthogonal to each other. Projector 650 may perform araster scan (horizontally or vertically), a bi-resonant scan, or anycombination thereof. In some embodiments, projector 650 may perform acontrolled vibration along the horizontal and/or vertical directionswith a specific frequency of oscillation to scan along two dimensionsand generate a two-dimensional projected image of the media presented touser's eyes. In other embodiments, projector 650 may include a lens orprism that may serve similar or the same function as one or morescanning mirrors. In some embodiments, image source assembly 610 may notinclude a projector, where the light emitted by light source 642 may bedirectly incident on the waveguide display.

As described above, an array of light emitters, such as a micro-LEDarray, may be used as a light source to generate display images, wherethe micro-LEDs in the micro-LED array may be individually controlled togenerate pixels of the display images. To form individual micro-LEDs inthe micro-LED array, am array of mesa structures may be etched in atleast some of the epitaxial layers of semiconductor materials. Each mesastructure may be further processed to add, for example, a p-contact, ann-contact, a passivation layer, and/or some light extraction structures(e.g., back and sidewall reflectors and a micro-lens), thereby forming amicro-LED.

FIG. 7A illustrates an example of an LED 700 having a vertical mesastructure. LED 700 may be a light emitter in light source 510, 540, or642. LED 700 may be a micro-LED made of inorganic materials, such asmultiple layers of semiconductor materials. The layered semiconductorlight emitting device may include multiple layers of III-V semiconductormaterials. A III-V semiconductor material may include one or more GroupIII elements, such as aluminum (Al), gallium (Ga), or indium (In), incombination with a Group V element, such as nitrogen (N), phosphorus(P), arsenic (As), or antimony (Sb). When the Group V element of theIII-V semiconductor material includes nitrogen, the III-V semiconductormaterial is referred to as a III-nitride material. The layeredsemiconductor light emitting device may be manufactured by growingmultiple epitaxial layers on a substrate using techniques such asvapor-phase epitaxy (VPE), liquid-phase epitaxy (LPE), molecular beamepitaxy (MBE), or metalorganic chemical vapor deposition (MOCVD). Forexample, the layers of the semiconductor materials may be grownlayer-by-layer on a substrate with a certain crystal lattice orientation(e.g., polar, nonpolar, or semi-polar orientation), such as a GaN, GaAs,or GaP substrate, or a substrate including, but not limited to,sapphire, silicon carbide, silicon, zinc oxide, boron nitride, lithiumaluminate, lithium niobate, germanium, aluminum nitride, lithiumgallate, partially substituted spinels, or quaternary tetragonal oxidessharing the beta-LiAlO₂ structure, where the substrate may be cut in aspecific direction to expose a specific plane as the growth surface.

In the example shown in FIG. 7A, LED 700 may include a substrate 710,which may include, for example, a sapphire substrate or a GaN substrate.A semiconductor layer 720 may be grown on substrate 710. Semiconductorlayer 720 may include a III-V material, such as GaN, and may be p-doped(e.g., with Mg, Ca, Zn, or Be) or n-doped (e.g., with Si or Ge). One ormore active layers 730 may be grown on semiconductor layer 720 to forman active region. Active layer 730 may include III-V materials, such asone or more InGaN layers, one or more AlInGaP layers, and/or one or moreGaN layers, which may form one or more heterostructures, such as one ormore quantum wells or MQWs. A semiconductor layer 740 may be grown onactive layer 730. Semiconductor layer 740 may include a III-V material,such as GaN, and may be p-doped (e.g., with Mg, Ca, Zn, or Be) orn-doped (e.g., with Si or Ge). One of semiconductor layer 720 andsemiconductor layer 740 may be a p-type layer and the other one may bean n-type layer. Semiconductor layer 720 and semiconductor layer 740sandwich active layer 730 to form the light emitting region. Forexample, LED 700 may include a layer of InGaN situated between a layerof p-type GaN doped with magnesium and a layer of n-type GaN doped withsilicon or oxygen. In some embodiments, LED 700 may include a layer ofAlInGaP situated between a layer of p-type AlInGaP doped with zinc ormagnesium and a layer of n-type AlInGaP doped with selenium, silicon, ortellurium.

In some embodiments, an electron-blocking layer (EBL) (not shown in FIG.7A) may be grown to form a layer between active layer 730 and at leastone of semiconductor layer 720 or semiconductor layer 740. The EBL mayreduce the electron leakage current and improve the efficiency of theLED. In some embodiments, a heavily-doped semiconductor layer 750, suchas a P⁺ or P⁺⁺ semiconductor layer, may be formed on semiconductor layer740 and act as a contact layer for forming an ohmic contact and reducingthe contact impedance of the device. In some embodiments, a conductivelayer 760 may be formed on heavily-doped semiconductor layer 750.Conductive layer 760 may include, for example, an indium tin oxide (ITO)or Al/Ni/Au film. In one example, conductive layer 760 may include atransparent ITO layer.

To make contact with semiconductor layer 720 (e.g., an n-GaN layer) andto more efficiently extract light emitted by active layer 730 from LED700, the semiconductor material layers (including heavily-dopedsemiconductor layer 750, semiconductor layer 740, active layer 730, andsemiconductor layer 720) may be etched to expose semiconductor layer 720and to form a mesa structure that includes layers 720-760. The mesastructure may confine the carriers within the device. Etching the mesastructure may lead to the formation of sidewalls 732 that may beorthogonal to the growth planes. A passivation layer 770 may be formedon sidewalls 732 of the mesa structure. Passivation layer 770 mayinclude an oxide layer, such as a SiO₂ layer, and may act as a reflectorto reflect emitted light out of LED 700. A contact layer 780, which mayinclude a metal layer, such as Al, Au, Ni, Ti, or any combinationthereof, may be formed on semiconductor layer 720 and may act as anelectrode of LED 700. In addition, another contact layer 790, such as anAl/Ni/Au metal layer, may be formed on conductive layer 760 and may actas another electrode of LED 700.

When a voltage signal is applied to contact layers 780 and 790,electrons and holes may recombine in active layer 730, where therecombination of electrons and holes may cause photon emission. Thewavelength and energy of the emitted photons may depend on the energybandgap between the valence band and the conduction band in active layer730. For example, InGaN active layers may emit green or blue light,AlGaN active layers may emit blue to ultraviolet light, while AlInGaPactive layers may emit red, orange, yellow, or green light. The emittedphotons may be reflected by passivation layer 770 and may exit LED 700from the top (e.g., conductive layer 760 and contact layer 790) orbottom (e.g., substrate 710).

In some embodiments, LED 700 may include one or more other components,such as a lens, on the light emission surface, such as substrate 710, tofocus or collimate the emitted light or couple the emitted light into awaveguide. In some embodiments, an LED may include a mesa of anothershape, such as planar, conical, semi-parabolic, or parabolic, and a basearea of the mesa may be circular, rectangular, hexagonal, or triangular.For example, the LED may include a mesa of a curved shape (e.g.,paraboloid shape) and/or a non-curved shape (e.g., conic shape). Themesa may be truncated or non-truncated.

FIG. 7B is a cross-sectional view of an example of an LED 705 having aparabolic mesa structure. Similar to LED 700, LED 705 may includemultiple layers of semiconductor materials, such as multiple layers ofIII-V semiconductor materials. The semiconductor material layers may beepitaxially grown on a substrate 715, such as a GaN substrate or asapphire substrate. For example, a semiconductor layer 725 may be grownon substrate 715. Semiconductor layer 725 may include a III-V material,such as GaN, and may be p-doped (e.g., with Mg, Ca, Zn, or Be) orn-doped (e.g., with Si or Ge). One or more active layer 735 may be grownon semiconductor layer 725. Active layer 735 may include III-Vmaterials, such as one or more InGaN layers, one or more AlInGaP layers,and/or one or more GaN layers, which may form one or moreheterostructures, such as one or more quantum wells. A semiconductorlayer 745 may be grown on active layer 735. Semiconductor layer 745 mayinclude a III-V material, such as GaN, and may be p-doped (e.g., withMg, Ca, Zn, or Be) or n-doped (e.g., with Si or Ge). One ofsemiconductor layer 725 and semiconductor layer 745 may be a p-typelayer and the other one may be an n-type layer.

To make contact with semiconductor layer 725 (e.g., an n-type GaN layer)and to more efficiently extract light emitted by active layer 735 fromLED 705, the semiconductor layers may be etched to expose semiconductorlayer 725 and to form a mesa structure that includes layers 725-745. Themesa structure may confine carriers within the injection area of thedevice. Etching the mesa structure may lead to the formation of mesaside walls (also referred to herein as facets) that may be non-parallelwith, or in some cases, orthogonal, to the growth planes associated withcrystalline growth of layers 725-745.

As shown in FIG. 7B, LED 705 may have a mesa structure that includes aflat top. A dielectric layer 775 (e.g., SiO₂ or SiNx) may be formed onthe facets of the mesa structure. In some embodiments, dielectric layer775 may include multiple layers of dielectric materials. In someembodiments, a metal layer 795 may be formed on dielectric layer 775.Metal layer 795 may include one or more metal or metal alloy materials,such as aluminum (Al), silver (Ag), gold (Au), platinum (Pt), titanium(Ti), copper (Cu), or any combination thereof. Dielectric layer 775 andmetal layer 795 may form a mesa reflector that can reflect light emittedby active layer 735 toward substrate 715. In some embodiments, the mesareflector may be parabolic-shaped to act as a parabolic reflector thatmay at least partially collimate the emitted light.

Electrical contact 765 and electrical contact 785 may be formed onsemiconductor layer 745 and semiconductor layer 725, respectively, toact as electrodes. Electrical contact 765 and electrical contact 785 mayeach include a conductive material, such as Al, Au, Pt, Ag, Ni, Ti, Cu,or any combination thereof (e.g., Ag/Pt/Au or Al/Ni/Au), and may act asthe electrodes of LED 705. In the example shown in FIG. 7B, electricalcontact 785 may be an n-contact, and electrical contact 765 may be ap-contact. Electrical contact 765 and semiconductor layer 745 (e.g., ap-type semiconductor layer) may form a back reflector for reflectinglight emitted by active layer 735 back toward substrate 715. In someembodiments, electrical contact 765 and metal layer 795 include samematerial(s) and can be formed using the same processes. In someembodiments, an additional conductive layer (not shown) may be includedas an intermediate conductive layer between the electrical contacts 765and 785 and the semiconductor layers.

When a voltage signal is applied across electrical contacts 765 and 785,electrons and holes may recombine in active layer 735. The recombinationof electrons and holes may cause photon emission, thus producing light.The wavelength and energy of the emitted photons may depend on theenergy bandgap between the valence band and the conduction band inactive layer 735. For example, InGaN active layers may emit green orblue light, while AlInGaP active layers may emit red, orange, yellow, orgreen light. The emitted photons may propagate in many differentdirections, and may be reflected by the mesa reflector and/or the backreflector and may exit LED 705, for example, from the bottom side (e.g.,substrate 715) shown in FIG. 7B. One or more other secondary opticalcomponents, such as a lens or a grating, may be formed on the lightemission surface, such as substrate 715, to focus or collimate theemitted light and/or couple the emitted light into a waveguide.

FIG. 8A illustrates an example of a micro-LED 800 with a mesa structure805. Micro-LED 800 may be an example of LED 700 or 705. Micro-LED 800may include an n-type semiconductor layer 820 epitaxially grown on asubstrate 810 that may be similar to substrate 710 or 715. In oneexample, substrate 810 may include a GaN substrate or a sapphiresubstrate with a buffer layer, and n-type semiconductor layer 820 mayinclude a GaN layer doped with, for example, Si or Ge. In anotherexample, substrate 810 may include a GaAs substrate. In the illustratedexample, n-type semiconductor layer 820 may be partially etched during amesa formation process after the epitaxially layers are grown, wheremesa structure 805 may include at least a portion 830 of n-typesemiconductor layer 820. One or more epitaxial layers, such as GaNbarrier layers and InGaN quantum well layers, or AlGaInP barrier layersand GaInP quantum well layers, may be grown on n-type semiconductorlayer 820 to form active layers 840 that includes one or more quantumwells. A p-type semiconductor layer 850 may be grown on active layers840. P-type semiconductor layer 850 may be doped with, for example, Mg,Ca, Zn, or Be. The layer stack may then be etched to form individualmesa structures 805 that each include a p-type semiconductor region, anactive region that includes active layers 840, and an n-typesemiconductor region. Mesa structure 805 may have a lateral lineardimension less than about 100 μm, less than about 50 μm, less than about20 μm, less than about 10 μm, less than about 5 μm, less than about 3μm, less than about 2 μm, or smaller. P-contacts 860 and n-contacts 870may be formed on the p regions and the exposed n regions of n-typesemiconductor layer 820. Each p-contact 860 may include, for example, ametal layer (e.g., Al, Au, Ni, Ti, or any combination thereof), or anindium tin oxide (ITO) and/or Al/Ni/Au film. In some embodiments,p-contact 860 may form a metal reflector to reflect emitted lighttowards n-type semiconductor layer 820. Each n-contact 870 may alsoinclude a layer of a metal material, such as Al, Au, Ni, Ti, or anycombination thereof.

Even though not shown in FIG. 8A, a passivation layer, such as an oxidelayer (e.g., a SiO₂ layer) or another dielectric layer, may be formed onsidewalls of mesa structure 805. The passivation layer may have a lowerrefractive index than the active region and may function as a reflector(e.g., due to total internal reflection) to reflect certain emittedlight out of micro-LED 800 as described above. As described above, insome embodiments, a metal layer may be formed on the passivation layerto form a sidewall metal reflector. Even though FIG. 8A shows a verticalmesa structure, micro-LED 800 may have a different mesa shape, such as aconical, parabolic, inward-tilted, or outward-tilted mesa shape.

When a voltage or current signal is applied to p-contact 860 andn-contact 870, holes and electrons may be injected into active layers840 from p-type semiconductor layer 850 and portion 830 of n-typesemiconductor layer 820, respectively. The electrons and holes mayrecombine in the quantum wells of active layers 840, where therecombination of electrons and holes may cause photon emission. Theemitted photons may be reflected by the passivation layer and/or themetal reflector, and may exit micro-LED 800 from the bottom (e.g.,n-type semiconductor layer 820 side) or the top (e.g., p-contact 860side). At the sidewalls of the mesa structure, active layers 840 mayhave a higher density of defects, such as dislocations, dangling bonds,pores, grain boundaries, vacancies, inclusion of precipitates, and thelike, due to the abrupt ending of the lattice structure and the etching.Thus, holes and electrons injected into the quantum wells of activelayers 840 may recombine at the defect sites, without generatingphotons. As such, there may be a high leakage at the mesa side wall, andthe internal/external quantum efficiency of micro-LED 800 may be low, atleast due to the losses caused by the non-radiative surfacerecombination.

FIG. 8B illustrates a simplified energy band structure of the activelayers in the active region of the example of micro-LED 800 shown inFIG. 8A. A curve 880 in FIG. 8B shows the conduction band of the activeregion and a curve 890 shows the valence band of the active region. Theactive region of micro-LED 800 may include multiple quantum well layerseach sandwiched by two barrier layers. In the example shown in FIG. 8B,the conduction band and the valence band of a barrier layer are shown bya level 882 and a level 892, respectively, and the conduction band andthe valence band of a quantum well layer are shown by a level 884 and alevel 894, respectively. As illustrated, the quantum well layer may havea lower bandgap between the conduction band and the valence band thanthe barrier layer. Thus, carriers (electrons and holes) injected intothe active region may be confined by the energy barriers to the quantumwell layers, where the electrons and holes may recombine to emit light.The wavelength of the emitted light may depend on the bandgap of thelight emitting layers (e.g., the quantum well layers). For example, inan InGaN LED, the energy bandgap of the barrier layers (e.g., GaN layer)may be higher than the energy bandgap of the quantum well layers (e.g.,InGaN layers), which may decrease (and thus the wavelength of theemitted light may increase) as the proportion of Indium in InGaNincreases.

In semiconductor LEDs, the internal quantum efficiency (IQE) is theratio between the number of photons emitted and the number of carriers(electrons and holes) injected in the active region. The generated lightmay be extracted from the LEDs in a particular direction or within aparticular solid angle. The ratio between the number of emitted photonsextracted from an LED and the number of electrons passing through theLED is referred to as the external quantum efficiency (EQE), whichdescribes how efficiently the LED converts injected electrons to photonsthat are extracted from the LED. The external quantum efficiency may beproportional to the injection efficiency, the internal quantumefficiency, and the extraction efficiency. The injection efficiencyrefers to the proportion of electrons passing through the device thatare injected into the active region. The extraction efficiency is theproportion of photons generated in the active region that escape fromthe device.

The quantum efficiency of LEDs depends on the relative rates ofcompetitive radiative (light producing) recombination and non-radiative(lossy) recombination that occur in the active region of the LEDs.Non-radiative recombination processes in the active region includeShockley-Read-Hall (SRH) recombination at defect sites, andelectron-electron-hole (eeh) and/or electron-hole-hole (ehh) Augerrecombination. The Auger recombination is a non-radiative processinvolving three carriers, which affects all sizes of LEDs. The internalquantum efficiency of an LED may be determined by:

${{IQE} = \frac{{BN}^{2}}{{AN} + {BN}^{2} + {CN}^{3}}},$

where A, B and C are the rates of SRH recombination, bimolecular(radiative) recombination, and Auger recombination, respectively, and Nis the charge-carrier density (i.e., charge-carrier concentration) inthe active region.

At the mesa sidewalls, the defect density of the active region may bevery high due to the abrupt ending of the lattice structure, chemicalcontamination, structural damages (e.g., due to dry etch), and the like.Therefore, the non-radiative recombination (e.g., SRH recombination)rate may be high at the mesa sidewalls. For traditional, broad area LEDsused in lighting and backlighting applications (e.g., with a lateraldevice area about 0.1 mm² to greater than about 1 mm²), the sidewallsare at the far ends of the devices. The devices can be designed suchthat little or no current is injected into regions within a minoritycarrier diffusion length from the mesa sidewalls, and thus the sidewallsurface area to volume ratio and the overall rate of SRH recombinationmay be low.

However, in micro-LEDs where the lateral size (e.g., a diameter or side)of the mesa structure of each micro-LED may be comparable to theminority carrier diffusion length, a larger proportion of the activeregion may be within a distance less than the minority carrier diffusionlength from the mesa sidewalls, where the defect density and thedefect-induced non-radiative recombination rate may be high. Therefore,a larger proportion of the injected carriers may diffuse to the regionsnear the sidewall surfaces, where they may be subjected to a higher SRHrecombination rate. This may cause the efficiency of the micro-LED todecrease, in particular at low current injection, and/or may cause thepeak efficiency of the micro-LED to decrease and/or the peak efficiencyoperating current to increase. Increasing the current injection tooperate closer to the peak efficiency may cause the efficiencies of themicro-LEDs to drop due to the higher eeh or ehh Auger recombination rateat a higher current density. Thus, the increased surface area to volumeratio in micro-LEDs may lead to a high non-radiative recombination rate,because a greater proportion of the total active region may fall withinthe minority carrier diffusion length from the micro-LED sidewalls. Thiscan cause the leakage current of the LED to increase and the efficiencyof the LED to decrease as the size of the LED decreases and/or cause thepeak efficiency operating current to increase, as the size of the LEDdecreases. For example, for a first LED with a 100 μm×100 μm×2 μm mesa,the side-wall surface area to volume ratio may be about 0.04. However,for a second LED with a 5 μm×5 μm×2 μm mesa, the side wall surface areato volume ratio may be about 0.8, which is about 20 times higher thanthe first LED. Thus, with a similar surface defect density, the SRHrecombination coefficient of the second LED may be about 20 times higheras well. Therefore, the efficiency of the second LED may besignificantly lower than the first LED.

FIG. 9 illustrates an example of a micro-LED 900 including a metal layer924 acting as both the p-contact and a back reflector. Micro-LED 900 mayinclude a mesa structure 920 formed on or in epitaxial layers 910. Asdescribed above with respect to FIGS. 7A-8B, epitaxial layers 910 mayinclude an n-type semiconductor layer (e.g., n-type semiconductor layer820, such an n-type GaN or another III-V semiconductor material layer),an active region (e.g., active layers 840, such as one or more InGaN/GaNlayers or other III-V semiconductor material layers), and a p-typesemiconductor layer (e.g., p-type semiconductor layer 850, such as ap-type GaN or another III-V semiconductor material layer). Mesastructure 920 may include a portion 922 of epitaxial layers 910, wherethe portion 922 may include at least a portion of the n-typesemiconductor layer, the active region, and the p-type semiconductorlayer.

Metal layer 924 may be formed on portion 922 (e.g., on the p-typesemiconductor layer) of epitaxial layers 910. Metal layer 924 mayfunction as the p-contact of micro-LED 900. Metal layer 924 may includea material that may have high electrical conductivity and high opticalreflectivity, such as silver, aluminum, or other suitable metals ormetal alloys. In one example, metal layer 924 may include silver due toits high achievable reflectance and high conductance. However, silvermay have a high rate of diffusion into semiconductor layers (e.g., theInGaN/GaN layers) at the mesa sidewall regions. Thus, a high leakagecurrent may occur at the sidewall regions of mesa structure 920. Toreduce the silver diffusion into the semiconductor layers and thus theleakage current, a barrier layer 926 may be formed on the top andsidewalls of metal layer 924. Barrier layer 926 may also need to beconductive in order to connect metal layer 924 to a control or drivercircuit. Barrier layer 926 may include, for example, titanium, tungsten,and the like. Barrier layer 926 may need to have a certain thickness inorder to reduce the diffusion of silver into the semiconductor layers. Adielectric layer 928 may be deposited on the top and sidewall regions ofmesa structure 920 to provide additional isolation. Barrier layer 926can be used as an etch stop layer to etch vias in dielectric layer 928.The vias may then be filled with a bonding material to form metal plugs930. The bonding material may include a metal, such as copper, forbonding micro-LED 900 to a wafer or die that includes LED drivercircuits fabricated thereon as described below with respect to, forexample, FIGS. 17A-19 .

For a micro-LED array with a small pitch, such as less than about 4 μmor less than about 3 μm, the linear lateral dimension D1 of mesastructure 920 may be less than about 2 μm, such as less than about 1.5μm. As such, the lateral size D2 of metal layer 924 and the width ofbarrier layer 926 at the sidewalls of metal layer 924 may need to bereduced. As described above, barrier layer 926 may need to have acertain thickness in order to reduce the current leakage at the edges ofmesa structure 920. In addition, dielectric layer 928 may also need touse some regions of the mesa structure. For small pitch micro-LEDs, thelateral dimensions of metal layer 924 and barrier layer 926 may be verysmall, thus leaving very little margin for alignment error during thesubsequent fabrication processes. For example, opening apertures indielectric layer 928 to form metal plugs 930 for making electricalcontacts with metal layer 924 via barrier layer 926 may reach thelithographic limit and may need very precise alignment, since thelateral size of the apertures (and metal plugs 930) may need to besmaller than the lateral size of barrier layer 926. In addition, whenthe pitch of the micro-LED array is reduced, the lateral size of metallayer 924 may need to be reduced more in order to leave sufficient roomfor barrier layer 926 and dielectric layer 928 at the sidewalls of metallayer 924 to maintain a low leakage. For example, for a micro-LED arraywith a pitch about 4 μm or smaller, the lateral size of metal layer 924may need to be reduced to less than about 80% or less than about 66% ofthe lateral size of the active region or the mesa structure. In oneexample, the lateral size of the active region may be about 1.2 μm,while the lateral size of metal layer 924 may need to be reduced toabout 0.8 μm or smaller. Reducing the size of metal layer 924 for thep-contact may increase the resistance of the p-contact. Moreover, asdescribed above, metal layer 924 is also used as a reflector at the pside to reflect light emitted in the action region towards the n-typesemiconductor layer of micro-LED 900, such that the emitted light may beextracted out of micro-LED 900. When the size of metal layer 924 isreduced, the overall reflectivity at the side of the p-typesemiconductor layer of micro-LED 900 may decrease, such that moreemitted photons may not be coupled out of micro-LED 900 from the side ofthe n-type semiconductor layer, thereby reducing the amount of collectedlight and the EQE.

Distribute Bragg reflectors (DBRs) may be used in some light emittingdevices, such as some LEDs (e.g., resonant cavity LEDs) andvertical-cavity surface-emitting lasers (VCSELs), to reflect lightand/or form a resonant cavity. A DBR may include alternated layers ofhigh-index and low-index materials, such as TiO₂ and SiO₂, where eachlayer may have an optical thickness, for example, about a quarter of thetarget wavelength for normal incidence. For the target wavelength, theoptical path length difference between the reflections at adjacentinterfaces between the layers is about a half of the target wavelength,and the reflection coefficients at the adjacent interfaces may havealternating signs due to the alternating refractive indices. Therefore,the reflected light from the interfaces may constructively interfere,thereby resulting in a high reflectance. The reflectivity of a DBR canbe higher when the difference in refractive index between the high-indexand the low-index layers (referred to herein as refractive indexcontrast or just index contrast) is higher and/or when the number ofpairs of the high-index and the low-index layers is larger.

DBRs made of dielectric materials, such as TiO₂ and SiO₂, are generallynot electrically conductive. Conductive DBRs may be formed usingepitaxially grown semiconductor layers with alternating dopingdensities, which generally have low refractive index contrast. Inaddition, some of these semiconductor materials may not be transparentto the emitted light due to high absorption. For large pitch lightemitting devices, a DBR made of dielectric layers can be used inconjunction with metal plugs that pass through the dielectric layers toform reflective electrical contacts. For small pitch light emittingdevices, the size of the metal plugs may reach the lithographic limit.In addition, it can be difficult to etch the high aspect ratio aperturesthrough the dielectric layers and to fill the large aspect ratioapertures with metal plugs. Furthermore, a transparent current spreadinglayer, such as an ITO layer, may need to be formed under the dielectricDBRs to improve the electrical connectivity.

According to certain embodiments, a conductive DBR made of transparentconductive material may be used as the electrical contact (e.g., thep-contact), the back reflector, and the current spreading layer. In someexamples, the conductive DBR includes layers of a same transparentconductive oxide (e.g., ITO, IZO (Indium Zinc Oxide), or AZO (AluminumZinc Oxide)), where the layers may have alternating refractive indicescaused by different porosities and/or nanorod orientations of thetransparent conductive oxide. For example, the conductive DBR mayinclude a set of crystalline ITO layers (e.g., having a first refractiveindex that may be tuned to an appropriate value, such as about 2.2 oranother desired value, by changing the porosity of the ITO layers)interleaved with a set of porous ITO layers (e.g., having a secondrefractive index that may be tuned to an appropriate value, such asabout 1.5 or another desired value, by changing the porosity of the ITOlayers). In some embodiments, the conductive DBR may include layers ofdifferent transparent conductive oxides that have different refractiveindices. Due to the high refractive index contrast between adjacentlayers, the conductive DBR can achieve a high reflectance (e.g., >90%or >95%, such as close to 99% or 100%, which is tunable by changing thenumber of layers) using a relatively small number of layers, and thusmay have a low overall thickness and also a low resistance.

Furthermore, because no metal p-contact reflector (e.g., a silver layer)is used, the barrier layer (e.g., barrier layer 926 shown in FIG. 9 )for the diffusive reflective metal would not be needed. As such, theconductive DBR can have about the same lateral size as the epitaxiallayers in the mesa structure to reduce the contact resistance andincrease the overall reflectance of the back reflector at the electricalcontact (e.g., the p-contact), such that almost all emitted lightpassing through the p-type semiconductor layer may be reflected backtowards the n-type semiconductor layer and the light emitting surface ofthe LED.

In addition, because the conductive DBR has about the same lateral sizeas the epitaxial layers in the mesa structure, the conductive DBR layerand the epitaxial layers can be etched in a same etching process ordifferent etching steps using a same etch mask to form the individualmesa structures. Therefore, no alignment may be needed to form theconductive DBR on the epitaxial layers in each mesa structure.

As such, for the LED structures disclosed herein, the pitch and the mesasize may not be restricted by the thickness of the barrier layer and/orthe lithographic limit associated with the fabrication of the metallayer (e.g., metal layer 924), the barrier layer (e.g., barrier layer926), the dielectric layer (e.g., dielectric layer 928), and/or themetal plugs described above. In addition, the risk of misalignmentsduring the fabrication of the mesa structures, the reflectors, and theelectrical contacts may be eliminated. Therefore, the pitch and the mesasize of the LEDs may be reduced to small values and the LEDs may stillbe reliably fabricated. Furthermore, since the conductive DBR acts asthe electrical contact (e.g., the p-contact), the current spreadinglayer, and the back reflector that can cover the whole active region ofthe mesa structure to reflect all light passing through the p-typesemiconductor layer, a high total reflectance and low resistance maystill be achieved even if the pitch and the mesa size of the micro-LEDsare reduced to small values, such as a few microns or about one micron.Thus, the micro-LED structures disclosed herein are highly scalable, andmay be well suited for small-pitch micro LEDs, such as micro-LEDs withpitches less than about 4 μm or less than about 3 μm.

FIG. 10 illustrates an example of a micro-LED device 1000 including aconductive DBR structure acting as both the p-contact and a backreflector according to certain embodiments. Micro-LED device 1000 mayinclude an array of micro-LEDs 1005 formed on epitaxial layers 1010. Asdescribed above with respect to FIGS. 7A-8 , epitaxial layers 1010 mayinclude an n-type semiconductor layer (e.g., n-type semiconductor layer820, such an n-type GaN or another III-V semiconductor material layer),an active region (e.g., active layers 840, such as one or more InGaN/GaNlayers or other III-V semiconductor material layers), and a p-typesemiconductor layer (e.g., p-type semiconductor layer 850, such as ap-type GaN or another III-V semiconductor material layer). ConductiveDBR layers 1020 may be formed on epitaxial layers 1010 and may includetransparent conductive oxide layers having alternating refractiveindices as described above and in more details below. An oxide layer1030 may be formed on conductive DBR layers 1020.

Oxide layer 1030, conductive DBR layers 1020, and at least a portion ofepitaxial layers 1010 that may include the p-type semiconductor layer,the active region, and a portion of the n-type semiconductor layer maybe etched in a same etch step or in multiple etch steps but using thesame etch mask to form individual mesa structures for individualmicro-LEDs 1005. As such, a conductive DBR structure etched inconductive DBR layers 1020 may fully cover the epitaxial layers in eachmesa structure as shown in FIG. 10 , or may cover at least 80% or atleast 90% of the lateral region of the epitaxial layers. A dielectriclayer 1032 (e.g., a passivation layer, such as SiO₂) may be deposited onthe top and the sidewalls of the mesa structures. The regions betweenthe mesa structures may be etched to expose the n-type semiconductorlayer in epitaxial layers 1010. A metal layer 1040 (e.g., an aluminumlayer) may be formed on the sidewalls of dielectric layer 1032, on thesurfaces of the exposed n-type semiconductor layer, and on top of someregions of dielectric layer 1032. Metal layer 1040 may be used as acurrent spreading layer and n-contacts for micro-LEDs 1005, and may alsoform sidewall reflectors for coupling the emitted light out ofmicro-LEDs 1005.

Metal plugs 1060 may be formed in dielectric layers 1032 and 1030 andmay contact conductive DBR layer 1020. Metal plugs 1060 may act as thep-electrodes and may be used to bond with bonding pads or traces on awafer or die that includes LED driver circuits fabricated thereon asdescribed below with respect to, for example, FIGS. 17A-19 . Metal plugs1070 may also be formed in dielectric layers 1032 and 1030 to connectwith metal layer 1040, which is electrically connected to n-typesemiconductor layer of micro-LEDs 1005 as described above. Metal plugs1070 may act as the n-electrodes and may be used to bond with bondingpads or traces on the wafer or die that includes LED driver circuitsfabricated thereon as described below with respect to, for example,FIGS. 17A-19 .

Light extraction structures 1080, such as micro-lenses and/orantireflective coating layers, may be formed on the side of the n-typesemiconductor layer in epitaxial layers 1010. Light extractionstructures 1080 may be etched in epitaxial layers 1010 and/or thesubstrate on which epitaxial layers 1010 are grown, or may be formed ina dielectric, semiconductor, or organic material layer deposited on then-type semiconductor layer of epitaxial layers 1010 (e.g., afterremoving or thinning the substrate on which epitaxial layers 1010 aregrown).

FIG. 11A illustrates an example of a conductive DBR structure 1110including transparent and conductive ITO thin films having differentnanorod orientations according to certain embodiments. Conductive DBRstructure 1110 may be an example of the conductive DBR structure shownin FIG. 10 . In the illustrated example, conductive DBR structure 1110includes multiple (e.g., 6, 8, or more) pairs of layers 1112 and 1114.Layers 1112 may include ITO films with a certain nanorod orientation,while layers 1114 may include ITO films with a different nanorodorientation. Each of the ITO films of layers 1112 and 1114 may bedeposited on the underlying layer (e.g., epitaxial layers 1010) atangles ranging from, for example, about 0° to about ±75° usingdeposition techniques such as electron-beam evaporation. At large vaporincident angles, deposited nanorods may prevent deposition in areas ofthe underlying layer that are shadowed by the deposited nanorods,thereby forming a porous ITO film. The feature sizes of the nanorods andthe voids between the nanorods in the porous ITO film may be smallcompared to the working wavelength, and thus the porous ITO film may bedescribed by an effective refractive index. In general, the larger thevapor incident angles, the larger the voids of the deposited ITO filmmay be, and thus the lower the effective refractive index of thedeposited ITO film may be. In some embodiments, the deposited ITO filmsmay be annealed in an oxygen atmosphere.

In one example, a first layer 1114 may include an ITO film deposited ata vapor incident angle about 75°, and may have an effective refractiveindex about 1.5 for light having a wavelength about 460 nm (blue light).A first layer 1112 may be deposited on the first layer 1114 at a vaporincident angle about −45°, and may include an ITO film having aneffective refractive index about 1.9 for light having a wavelength about460 nm (blue light). A second layer 1114 may then be deposited on thefirst layer 1112 at a vapor incident angle about 75° to form another lowrefractive index ITO film. A second layer 1112 may be deposited on thesecond layer 1114 at a vapor incident angle about −45° to form anotherhigh refractive index ITO film. The deposition process may be performedrepeatedly to form other pairs of layers 1114 and 1112. The number ofpairs of layers 1114 and 1112 used in conductive DBR structure 1110 maybe determined based on, for example, the desired reflectivity, therefractive index contrast between layer 1112 and layer 1114, the workingwavelength, the desired total thickness of the conductive DBR structure,and the like. As described above, the thickness of each layers 1112 and1114 may be selected such that the light reflected at the interfacesbetween the adjacent layers may constructively interfere to enhance thereflection.

FIG. 11B illustrates another example of a conductive DBR structure 1120including transparent conductive ITO thin films having differentporosities according to certain embodiments. Conductive DBR structure1120 may be an example of the conductive DBR structure shown in FIG. 10. In the illustrated example, conductive DBR structure 1120 includesmultiple (e.g., 4, 6, 8, or more) pairs of layers 1122 and 1124. Forexample, with a refractive index contrast about 0.7, a 90% reflectancecan be achieved using only 4 pairs of layers, which may have a totalthickness of about 520 nm, 590 nm, and 710 nm for blue, green, and redlight, respectively. Thinner DBR stacks can be easier to fabricate. When8 or more pairs of layers with refractive index contrast about 0.7 areused, the reflectance can be about 100%. Layers 1122 may include ITOfilms with a certain porosity, while layers 1114 may include ITO filmswith a different porosity. For example, each layer 1122 may include adense crystalline ITO thin film, whereas each layer 1124 may include aporous ITO thin film.

In one example, the dense crystalline ITO thin films (e.g., layers 1122)may be deposited by a long-throw radio frequency (RF) magnetronsputtering technique. In the long-throw RF sputtering process, thesputtered particles may be thermalized and may reach a substrate (e.g.,a wafer with epitaxial layers grown thereon) by diffusion when thetarget-to-substrate distance is large. The long-throw RF sputteringtechnique can achieve a high thickness uniformity of the deposited film.In addition, in the long-throw RF sputtering, the substrate can be at alow temperature because the target-to-substrate distance is large. Thedense crystalline ITO thin film formed by the long-throw RF sputteringprocess may have a high refractive index, such as about 2.2 for lighthaving a wavelength about 460 nm (blue light).

The porous ITO thin films (e.g., layers 1124) may be made by, forexample, extracting organic matters from gel-coated films using highpolarity supercritical CO₂ fluids that may include a small amount ofpolar cosolvents, such as Isopropyl alcohol (IPA), mixed with nonpolarCO₂ fluids. The mixed solvents may greatly enhance the solubility ofpolar solutes in the mixed solvents even at a low process temperature.Layers 1122 and 1124 may be alternately formed on the substrate to formconductive DBR structure 1120. The porous ITO thin film may have a lowrefractive index, such as about 1.51 for light having a wavelength about460 nm (blue light).

The number of pairs of layers 1124 and 1122 may be determined based on,for example, the desired reflectivity, the refractive index contrastbetween layer 1122 and layer 1124, the working wavelength, the desiredtotal thickness of conductive DBR structure 1120, and the like. Asdescribed above, the thickness of each layers 1122 and 1124 may beselected such that the light reflected at the interfaces between theadjacent layers may constructively interfere to achieve a highreflectance.

FIG. 12A includes a diagram 1200 illustrating the reflectance of anexample of a conductive DBR structure for blue light according tocertain embodiments. The conductive DBR structure may be an example ofconductive DBR structure 1120 and may include 8 pairs of layer 1122 andlayer 1124. The conductive DBR structure can be designed to reflect anytarget wavelength (e.g., UV, blue, green, red, etc.). In the illustratedexample, the conductive DBR structure may be designed for a targetwavelength about 460 nm. The refractive index of each layer 1122 may beabout 2.2 for the target wavelength, whereas the refractive index ofeach layer 1124 may be about 1.51 for the target wavelength. A curve1210 in diagram 1200 shows the reflectance of the conductive DBRstructure for different wavelengths. As illustrated, the conductive DBRstructure may have a reflectance close to about 100% at the targetwavelength.

FIG. 12B includes a diagram 1202 illustrating the reflectance of anexample of a conductive DBR structure for green light according tocertain embodiments. The conductive DBR structure may be an example ofconductive DBR structure 1120 and may include 8 pairs of layer 1122 andlayer 1124. In the illustrated example, the conductive DBR structure maybe designed for a target wavelength about 550 nm (green light). Therefractive index of each layer 1122 may be about 2.2 for the targetwavelength, whereas the refractive index of each layer 1124 may be about1.51 for the target wavelength. A curve 1212 in diagram 1202 shows thereflectance of the conductive DBR structure for different wavelengths.As illustrated, the conductive DBR structure may have a reflectanceclose to about 100% for green light.

FIG. 12C includes a diagram 1204 illustrating the reflectance of anexample of a conductive DBR structure for red light according to certainembodiments. The conductive DBR structure may be an example ofconductive DBR structure 1120 and may include 8 pairs of layer 1122 andlayer 1124. In the illustrated example, the conductive DBR structure maybe designed for a target wavelength about 650 nm (red light). Therefractive index of each layer 1122 may be about 2.2 for the targetwavelength, whereas the refractive index of each layer 1124 may be about1.51 for the target wavelength. A curve 1214 in diagram 1204 shows thereflectance of the conductive DBR structure for different wavelengths.As illustrated, the conductive DBR structure may have a reflectanceclose to about 100% for red light.

FIGS. 13A-13F illustrate an example of a self-aligned process forfabricating a micro-LED device including a conductive DBR structure,such as micro-LED device 1000, according to certain embodiments. FIG.13A shows a substrate 1310 that may include a base wafer (e.g., asilicon or sapphire wafer) with epitaxial layers formed thereon. Asdescribed above, the epitaxial layers may include, for example, anoptional buffer layer, an n-type semiconductor layer (e.g., an n-GaNlayer), active layers (e.g., one or more quantum well layers and one ormore barrier layers), and a p-type semiconductor layer (e.g., a p-GaNlayer). Conductive DBR layers 1320 may be formed on substrate 1310. Forexample, conductive DBR layers 1320 may be formed on the p-typesemiconductor layer of substrate 1310. An oxide layer 1330, such as aSiO₂ layer, may be deposited on conductive DBR layers 1320. In oneexample, oxide layer 1330 may have a thickness about 100 to about 200nm.

As described above, conductive DBR layers 1320 may include transparentconductive oxide layers (e.g., ITO, IZO, AZO, etc.) having alternatingrefractive indices. For example, conductive DBR layers 1320 may includea set of sputtered crystalline ITO thin films interleaved with a set ofporous ITO thin films as described above with respect to FIG. 11B. Thesputtered crystalline ITO thin films may have a high refractive index,such as about 2.2. The porous ITO thin films may have a low refractiveindex, such as about 1.51. Thus, a refractive index contrast about 0.7may be achieved, such that a smaller number of conductive DBR layers maybe used to achieve the desired reflectance. In another example,conductive DBR layers 1320 may include a set of ITO thin films (having afirst nanorod orientation and a low refractive index) interleaved with aset of ITO thin films having a different nanorod orientation and a highrefractive index as described above with respect to FIG. 11A. ConductiveDBR layers 1320 may include multiple pairs (e.g., more than 3 pairs,more than 5 pairs, or more than 6 pairs, such as 6 to 8 or more pairs)of a high refractive index transparent conductive oxide (e.g., sputteredcrystalline ITO) layer and a low refractive index transparent conductiveoxide (e.g., porous ITO) layer in order to achieve the desiredreflectance, such as greater than about 90%, greater than about 95%,greater than about 98%, greater than about 99%, or higher. The totalthickness of conductive DBR layers 1320 may be less than about 1 μm.

FIG. 13B shows that mesa structures 1302 may be etched in oxide layer1330, conductive DBR layers 1320, and at least a portion of substrate1310. The etching may be performed in a single dry etch step or inmultiple etch steps using the same etch mask. Thus, the conductive DBRstructure and the epitaxial layers in each mesa structure may have thesame or similar lateral dimension. For example, the conductive DBRstructure may cover at least 80% or at least 90% of the lateral regionof the epitaxial layers in each mesa structure. Mesa structures 1302 mayhave a small pitch, such as less than about 5 μm, less than about 4 μm,less than about 3 μm, less than about 2 μm, or smaller. The linearlateral size of mesa structures 1302 may be less than about 3 μm, lessthan about 2 μm, less than about 1.5 μm, or smaller.

FIG. 13C shows a dielectric layer 1332 (e.g., a SiO₂ layer) formed onthe top surfaces and the sidewall surfaces of mesa structures 1302.Dielectric layer 1332 may be conformally deposited on the top surfacesand the sidewall surfaces of mesa structures 1302 and the exposedsurfaces of the epitaxial layers in substrate 1310 by a depositionprocess, such as a chemical vapor deposition (CVD) or atomic layerdeposition (ALD) process. In some embodiments, dielectric layer 1332 maybe deposited to fill the gaps between mesa structures 1302 and may thenbe etched to form trenches in the regions between mesa structures 1302while leaving some dielectric materials on the sidewalls of mesastructures 1302. Dielectric layer 1332 at the bottom of the trenches inthe regions between mesa structures 1302 may be etched, for example,using the oxide (e.g., dielectric layer 1332) on top of mesa structures1302 as the etch mask, to expose the n-type semiconductor layer. In someembodiments, the n-type semiconductor layer may be further etched toform U-shaped, V-shaped, or parabolic shaped voids in the n-typesemiconductor layer for making n-contacts and sidewall reflectors in thesubsequent processes.

FIG. 13D shows that a metal layer 1340 may be conformally deposited onthe surfaces of mesa structure 1302 and the voids formed in the n-typesemiconductor layer. Metal layer 1340 may include a metal that has ahigh conductivity and a high reflectivity. In one example, metal layer1340 may include an aluminum layer. Metal layer 1340 may be patterned,for example, to remove metal layer 1340 in certain regions, such asmetal layer 1340 on the top of mesa structure 1302 for each micro-LED.Metal layer 1340 may function as a current spreading layer, then-contacts, and sidewall reflectors for the micro-LEDs.

FIG. 13E shows that a dielectric layer 1350 may be deposited on thestructure shown in FIG. 13D. Dielectric layer 1350 may include, forexample, a SiO₂ layer. Dielectric layer 1350 may be a thick dielectriclayer and may fill the gaps between metal layer 1340. The thickness ofdielectric layer 1350 on top of dielectric layer 1332 may be, forexample, about 1 μm.

FIG. 13F shows that dielectric layer 1350 (and layers 1330 and 1332) maybe etched to form apertures on top of mesa structures 1302, and theapertures may be filled with a metal (e.g., aluminum, titanium, copper,etc.) to form p-electrodes 1360 that contact the conductive DBRstructures formed in conductive DBR layers 1320. Similarly, some areasof dielectric layer 1350 may be etched to form apertures, and theapertures may be filled with a metal (e.g., aluminum, titanium, copper,etc.) to form one or more n-electrodes 1370 that contact metal layer1340.

FIG. 13F also shows that light extraction structures 1380, such asmicro-lenses, may be formed on the bottom side of substrate 1310 toimprove the light extraction efficiency. In some embodiments, lightextraction structures 1380 may be formed after the manufactured wafer isbonded to a CMOS backplane (e.g., a silicon wafer with driver andcontrol circuits fabricated thereon), and/or after the base wafer (e.g.,the silicon or sapphire wafer) is thinned or removed. Light extractionstructures 1380 may be etched in substrate 1310, or may be formed in adielectric, semiconductor, or organic material layer deposited on theside of the n-type semiconductor layer of the epitaxial layers.

FIGS. 14A-14F illustrate another example of a self-aligned process forfabricating a micro-LED device including a conductive DBR structureaccording to certain embodiments. FIG. 14A shows a substrate 1410 thatincludes a base wafer (e.g., a silicon or sapphire wafer) and epitaxiallayers formed thereon. As described above, the epitaxial layers mayinclude, for example, an optional buffer layer, an n-type semiconductorlayer (e.g., an n-GaN layer), active layers (e.g., one or more quantumwell layers and one or more barrier layers), and a p-type semiconductorlayer (e.g., a p-GaN layer). Conductive DBR layers 1420 may be formed onsubstrate 1410. For example, conductive DBR layers 1420 may be formed onthe p-type semiconductor layer of substrate 1410.

As described above, conductive DBR layers 1420 may include transparentconductive oxide layers (e.g., ITO, IZO, AZO, etc.) that havealternating refractive indices. For example, conductive DBR layers 1420may include a set of sputtered crystalline ITO thin films interleavedwith a set of porous ITO thin films as described above with respect toFIG. 11B. The sputtered crystalline ITO thin films may have a highrefractive index, such as about 2.2. The porous ITO thin films may havea low refractive index, such as about 1.51. Thus, a refractive indexcontrast about 0.7 may be achieved, such that a smaller number ofconductive DBR layers may be used to achieve the desired reflectance. Inanother example, conductive DBR layers 1420 may include a set of ITOthin films having a first nanorod orientation (and a low refractiveindex) interleaved with a set of ITO thin films with a different nanorodorientation (and a high refractive index) as described above withrespect to FIG. 11A. Conductive DBR layers 1420 may include multiplepairs (e.g., more than 3 pairs, more than 5 pairs, or more than 6 pairs,such as 6 to 8 or more pairs) of a high refractive index transparentconductive oxide (e.g., sputtered crystalline ITO) layer and a lowrefractive index transparent conductive oxide (e.g., porous ITO) layerin order to achieve the desired reflectance, such as greater than about90%, greater than about 95%, greater than about 98%, greater than about99%, or higher. The total thickness of conductive DBR layers 1420 may beless than about 1 μm.

FIG. 14B shows that mesa structures 1402 may be etched in conductive DBRlayers 1420 and at least a portion of substrate 1410. The etching may beperformed in a single dry etch step or in multiple etch steps using thesame etch mask. Thus, the conductive DBR structure formed in conductiveDBR layers 1420 and the epitaxial layers in each mesa structure may havethe same or similar lateral dimensions. For example, the conductive DBRstructure may cover at least 80% or at least 90% of the lateral regionof the epitaxial layers in each mesa structure. Mesa structures 1402 mayhave a small pitch, such as less than about 5 μm, less than about 4 μm,less than about 3 μm, less than about 2 μm, or smaller. The linearlateral size of mesa structures 1402 may be less than about 3 μm, lessthan about 2 μm, less than about 1.5 μm, or smaller.

FIG. 14C shows a dielectric layer 1430 (e.g., a SiO₂ layer) formed onthe top surfaces and the sidewall surfaces of mesa structures 1402, andon regions between mesa structures 1402. Dielectric layer 1430 mayfunction as a passivation and isolation layer at the sidewalls of mesastructures 1402. Dielectric layer 1430 may have a thickness, forexample, about 100 to about 200 nm. Dielectric layer 1430 may beconformally deposited on the top surfaces and the sidewall surfaces ofmesa structures 1402 by a deposition process, such as a CVD or ALDprocess. A metal layer 1440 may be conformally deposited on the surfacesof dielectric layer 1430. Metal layer 1440 may include a metal that hasa high conductivity and a high reflectivity. In one example, metal layer1440 may include an aluminum layer. Metal layer 1440 may be patterned,for example, to remove metal layer 1440 in certain regions, such asmetal layer 1440 on top of mesa structure 1402 for each micro-LED. Metallayer 1440 may function as a current spreading layer, n-contacts, andsidewall reflectors for the micro-LEDs.

FIG. 14D shows that a dielectric layer 1450 may be deposited on thestructure shown in FIG. 14D. Dielectric layer 1450 may include, forexample, a SiO₂ layer. Dielectric layer 1450 may be a thick dielectriclayer and may fill the gaps between metal layer 1440. The thickness ofdielectric layer 1450 on top of dielectric layer 1430 may be, forexample, about 1 μm.

FIG. 14E shows that dielectric layer 1450 and dielectric layer 1430 maybe etched to form apertures (e.g., trenches) on top of mesa structures1402, and the apertures may be filled with a metal (e.g., aluminum,titanium, copper, etc.) to form p-electrodes 1460 that contact theconductive DBR structures formed in conductive DBR layers 1420. In someembodiments, some areas of dielectric layer 1450 may be etched to formapertures, and the apertures may be filled with a metal (e.g., aluminum,titanium, copper, etc.) to form n-electrodes (not shown in FIG. 14E)that contact metal layer 1440.

FIG. 14F shows that light extraction structures 1470, such asmicro-lenses, may be formed on the bottom side of substrate 1410 toimprove the light extraction efficiency. In some embodiments, lightextraction structures 1470 may be formed after the manufactured wafer isbonded to a silicon wafer with driver and control circuits fabricatedthereon, and/or after the base wafer (e.g., the silicon or sapphirewafer) is thinned or removed. Light extraction structures 1470 may beetched in substrate 1410, or may be formed in a dielectric,semiconductor, or organic material layer deposited on the n-typesemiconductor layer.

In addition, substrate 1410 and dielectric layer 1430 may be etched fromthe side of the n-type semiconductor layer to expose metal layer 1440. Atransparent conductive oxide layer 1480 may then be formed on thesurfaces of light extraction structures 1470, the exposed surface ofsubstrate 1410 (e.g., the n-type semiconductor layer), and the exposedsurfaces of metal layer 1440, to form the n-contacts and a currentspreading layer for the n-contacts.

FIG. 15 includes a flowchart 1500 illustrating an example of aself-aligned process for fabricating a micro-LED device including aconductive DBR structure acting as both the electrical contact (e.g.,p-contact) and a back reflector according to certain embodiments. It isnoted that the operations illustrated in FIG. 15 provide particularprocesses for fabricating micro-LEDs. Other sequences of operations canalso be performed according to alternative embodiments. For example,alternative embodiments may perform the operation in a different order.Moreover, the individual operations illustrated in FIG. 15 can includemultiple sub-operations that can be performed in various sequences asappropriate for the individual operation. Furthermore, some operationscan be added or removed depending on the particular applications. Insome implementations, two or more operations may be performed inparallel. One of ordinary skill in the art would recognize manyvariations, modifications, and alternatives.

Operations in block 1510 of flowchart 1500 may include forming a layerstack on a substrate (e.g., a silicon or sapphire wafer). The layerstack may include a plurality of epitaxial layers and a plurality oftransparent conductive oxide layers that form a conductive DBR. Formingthe layer stack may include, at block 1512, growing the plurality ofepitaxial layers that includes an n-type semiconductor layer, an activeregion configured to emit visible light having a first wavelength, and ap-type semiconductor layer. Forming the layer stack may also include, atblock 1514, depositing the plurality of transparent conductive oxidelayers on the plurality of epitaxial layers. The plurality oftransparent conductive oxide layers may include a first set oftransparent conductive oxide layers characterized by a first refractiveindex, and a second set of transparent conductive oxide layerscharacterized by a second refractive index and interleaved with thefirst set of transparent conductive oxide layers, where a reflectance ofthe conductive DBR for the first wavelength is greater than 90%, greaterthan about 95%, or greater than about 98%. The first set of transparentconductive oxide layers may include a first set of ITO layers. Thesecond set of transparent conductive oxide layers may include a secondset of ITO layers. The first set of ITO layers and the second set of ITOlayers may have different porosities or different nanorod orientationsas described above. In some embodiments, a dielectric (e.g., oxide)layer may be formed on the conductive DBR.

Operations at block 1520 may include etching the layer stack to form anarray of mesa structures. The array of mesa structures may becharacterized by a pitch equal to or less than about 4 μm, less thanabout 3 μm, or less than about 2 μm. Each mesa structure may becharacterized by a linear lateral dimension less than about 3 μm, lessthan about 2 μm, or less than about 1.5 μm. The layer stack may beetched through the plurality of transparent conductive oxide layers andat least some of the plurality of epitaxial layers. For example, then-type semiconductor layer may be partially etched. The etching may beperformed in a single etch step or in multiple etch steps but using thesame etch mask. As such, the conductive DBR and the epitaxial layers ineach mesa structure may have similar or same lateral dimensions. Forexample, the conductive DBR may cover at least 80% or at least 90% ofthe lateral region of the epitaxial layers in each mesa structure.

At block 1530, a first dielectric layer (e.g., SiO₂) may be formed onsurfaces (e.g., top and sidewall surfaces) of the mesa structures andregions between the mesa structures. The first dielectric layer mayfunction as a passivation and isolation layer at the sidewalls of themesa structures. The first dielectric layer may have a thickness, forexample, about 100 to about 200 nm. The first dielectric layer may beconformally deposited on the top surfaces and the sidewall surfaces ofthe mesa structures by a deposition process, such as a CVD process or anALD process.

At block 1540, a patterned metal layer may be formed on surfaces of thefirst dielectric layer. For example, a metal layer may be conformallydeposited on the surfaces of the first dielectric layer. The metal layermay include a metal that has a high conductivity and a highreflectivity, such as aluminum. The metal layer may be patterned, forexample, to remove the metal layer in certain regions, such as the metallayer on top of the mesa structure for each micro-LED. The metal layermay function as a current spreading layer, n-contacts, and/or sidewallreflectors for the micro-LEDs.

At block 1550, the operation may include depositing a second dielectriclayer on the patterned metal layer and the first dielectric layer. Thesecond dielectric layer may include, for example, a SiO₂ layer. Thesecond dielectric layer may be a thick dielectric layer and may fill thegaps between the metal layer in regions between the mesa structures. Thethickness of the second dielectric layer on top of the first dielectriclayer may be, for example, about 1 μm.

Operations at block 1560 may include forming, in the dielectric layers,a first set of metal plugs (e.g., p-electrodes) contacting theconductive DBR and/or a second set of metal plugs (e.g., n-electrodes)contacting the patterned metal layer. For example, the dielectric layerson top of each mesa structure may be etched to form an aperture (e.g., atrench), and the aperture may be filled with a metal (e.g., aluminum,titanium, copper, etc.) to form a p-electrode that contacts theconductive DBR. In some embodiments, some areas of the second dielectriclayer on top of the patterned metal layer may be etched to formapertures, and the apertures may be filled with a metal (e.g., aluminum,titanium, copper, etc.) to form n-electrodes that contact the patternedmetal layer.

Optionally, at block 1570, light extraction structures, such asmicro-lenses, may be formed on the epitaxial layers (e.g., on the n-typesemiconductor layer). In some embodiments, the light extractionstructures may be formed after the processed wafer including themicro-LEDs is bonded to a silicon wafer (e.g., a CMOS backplane) withdriver and control circuits fabricated thereon, and/or after thesubstrate (e.g., the silicon or sapphire wafer) is thinned or removed.The CMOS backplane may have bonding pads formed thereon. Bonding pads onthe CMOS backplane and the metal plugs on the processed wafer or die maybe bonded together. In some embodiments, the gap between the wafer ordie including the micro-LEDs and the CMOS backplane may be filled with anon-conductive material, such as a dielectric material or an organicmaterial (e.g., an epoxy or a resin). In some embodiments, the surfaceof the CMOS backplane and the surface of the wafer or die including themicro-LEDs may each include a dielectric layer and the two dielectriclayers may also be bonded together in a hybrid bonding process. Thesubstrate of the micro-LEDs (e.g., the silicon or sapphire wafer) maythen be thinned or removed from the bonded device. The light extractionstructures (e.g., micro-lenses) may be formed on the light emitting sideof the bonded device. For example, the light extraction structures maybe etched in the epitaxial layers, or may be formed in a dielectric,semiconductor, or organic material layer deposited on the side of then-type semiconductor layer of the epitaxial layers.

Optionally, at block 1580, a transparent conductive layer (e.g., an ITOlayer) may be deposited on the light emitting side of the bonded device.In some embodiments, the epitaxial layers (e.g., the n-typesemiconductor layer) and the first dielectric layer in regions betweenthe mesa structures may be etched from the side of the n-typesemiconductor layer to expose the metal layer, before the transparentconductive layer is deposited. Thus, the transparent conductive layermay be electrically coupled to at least one of the patterned metallayer, the n-type semiconductor layer, or the second set of metal plugs(e.g., through the patterned metal layer). The transparent conductivelayer and/or the patterned metal layer may be used to spread the currentbetween the n-contacts of the micro-LEDs and the n-electrodes.

FIG. 16 includes a flowchart 1600 illustrating an example of aself-aligned process for fabricating a micro-LED device including aconductive DBR structure acting as both the electrical contact (e.g.,the p-contact) and a back reflector according to certain embodiments.Flowchart 1600 may be an example of flowchart 1500. It is noted that theoperations illustrated in FIG. 16 provide particular processes forfabricating micro-LEDs. Other sequences of operations can also beperformed according to alternative embodiments. For example, alternativeembodiments may perform the operation in a different order. Moreover,the individual operations illustrated in FIG. 16 can include multiplesub-operations that can be performed in various sequences as appropriatefor the individual operation. Furthermore, some operations can be addedor removed depending on the particular applications. In someimplementations, two or more operations may be performed in parallel.One of ordinary skill in the art would recognize many variations,modifications, and alternatives.

Operations in block 1610 of flowchart 1600 may include forming a layerstack on a substrate (e.g., a silicon or sapphire wafer). The layerstack may include a plurality of epitaxial layers and a plurality oftransparent conductive oxide layers that form a conductive DBR. Formingthe layer stack may include, at block 1612, growing the plurality ofepitaxial layers that includes an n-type semiconductor layer, an activeregion configured to emit visible light having a first wavelength, and ap-type semiconductor layer. Forming the layer stack may also include, atblock 1614, depositing the plurality of transparent conductive oxidelayers on the plurality of epitaxial layers. The plurality oftransparent conductive oxide layers may include a first set oftransparent conductive oxide layers characterized by a first refractiveindex, and a second set of transparent conductive oxide layerscharacterized by a second refractive index and interleaved with thefirst set of transparent conductive oxide layers, where a reflectance ofthe conductive DBR for the first wavelength is greater than 90%, greaterthan about 95%, or greater than about 98%. The first set of transparentconductive oxide layers may include a first set of ITO layers. Thesecond set of transparent conductive oxide layers may include a secondset of ITO layers. The first set of ITO layers and the second set of ITOlayers may have different porosities or different nanorod orientationsas described above. Forming the layer stack may also include, at block1616, depositing a first dielectric (e.g., oxide) layer on theconductive DBR.

Operations at block 1620 may include etching the layer stack to form anarray of mesa structures. The array of mesa structures may becharacterized by a pitch equal to or less than about 4 μm, less thanabout 3 μm, or less than about 2 μm. Each mesa structure may becharacterized by a linear lateral dimension less than about 3 μm, lessthan about 2 μm, or less than about 1.5 μm. The layer stack may beetched through the plurality of transparent conductive oxide layers andat least some of the plurality of epitaxial layers. For example, then-type semiconductor layer may be partially etched. The etching may beperformed in a single etch step or in multiple etch steps using the sameetch mask. As such, the conductive DBR and the epitaxial layers in eachmesa structure may have similar or same lateral dimensions. For example,the conductive DBR may cover at least 80% or at least 90% of the lateralregion of the epitaxial layers in each mesa structure.

At block 1630, a second dielectric layer (e.g., SiO₂) may be formed onsurfaces (e.g., top and sidewall surfaces) of the mesa structures andregions between the mesa structures. The second dielectric layer mayfunction as a passivation and isolation layer at the sidewalls of themesa structures. The second dielectric layer may have a thickness, forexample, about 100 to about 200 nm. The second dielectric layer may beconformally deposited on the top surfaces and the sidewall surfaces ofthe mesa structures by a deposition process, such as a CVD process or anALD process.

Optionally, at block 1632, the second dielectric layer at regionsbetween the mesa structures may be etched, for example, using the seconddielectric layer on top of the mesa structures as the etch mask, toexpose the n-type semiconductor layer at the regions between the mesastructures. In some embodiments, the n-type semiconductor layer may befurther etched to form U-shaped, V-shaped, or parabolic shaped voids inthe n-type semiconductor layer for making n-contacts and sidewallreflectors in the subsequent processes.

At block 1640, a patterned metal layer may be formed on surfaces of thesecond dielectric layer. For example, a metal layer may be conformallydeposited on the surfaces of the second dielectric layer and the voidsformed in the n-type semiconductor layer. The metal layer may include ametal that has a high conductivity and a high reflectivity, such asaluminum. The metal layer may be patterned, for example, to remove themetal layer in certain regions, such as the metal layer on top of themesa structure for each micro-LED. The metal layer may function as acurrent spreading layer, n-contacts, and sidewall reflectors for themicro-LEDs.

At block 1650, the operation may include depositing a third dielectriclayer on the patterned metal layer and the second dielectric layer. Thethird dielectric layer may include, for example, a SiO₂ layer. The thirddielectric layer may be a thick dielectric layer and may fill the gapsbetween the metal layer in regions between the mesa structures. Thethickness of the third dielectric layer on top of the second dielectriclayer may be, for example, about 1 μm.

Operations at block 1660 may include forming, in the dielectric layers,a first set of metal plugs (e.g., p-electrodes) contacting theconductive DBR and a second set of metal plugs (e.g., n-electrodes)contacting the patterned metal layer. For example, the dielectric layerson top of each mesa structure may be etched to form an aperture (e.g., atrench), and the aperture may be filled with a metal (e.g., aluminum,titanium, copper, etc.) to form a p-electrode that contacts theconductive DBR. In some embodiments, some areas of the dielectric layerson top of the patterned metal layer may be etched to form apertures, andthe apertures may be filled with a metal (e.g., aluminum, titanium,copper, etc.) to form one or more n-electrodes that contact thepatterned metal layer.

Optionally, at block 1670, light extraction structures, such asmicro-lenses, may be formed on the epitaxial layers (e.g., on the n-typesemiconductor layer). In some embodiments, the light extractionstructures may be formed after the processed wafer including themicro-LEDs is bonded to a silicon wafer (e.g., a CMOS backplane) withdriver and control circuits fabricated thereon, and/or after thesubstrate (e.g., the silicon or sapphire wafer) is thinned or removed.The CMOS backplane may have bonding pads formed thereon. Bonding pads onthe CMOS backplane and the metal plugs on the processed wafer or die maybe bonded together. In some embodiments, the gap between the wafer ordie including the micro-LEDs and the CMOS backplane may be filled with anon-conductive material, such as a dielectric material or an organicmaterial (e.g., an epoxy or a resin). In some embodiments, the surfaceof the CMOS backplane and the surface of the wafer or die including themicro-LEDs may each include a dielectric layer and the two dielectriclayers may be bonded together in a hybrid bonding process. The substrateof the micro-LEDs (e.g., the silicon or sapphire wafer) may then bethinned or removed from the bonded device. The light extractionstructures (e.g., micro-lenses) may be formed on the light emitting sideof the bonded device. For example, the light extraction structures maybe etched in the epitaxial layers, or may be formed in a dielectric,semiconductor, or organic material layer deposited on the side of then-type semiconductor layer of the epitaxial layers.

FIG. 17A illustrates an example of a method of die-to-wafer bonding forarrays of LEDs according to certain embodiments. In the example shown inFIG. 17A, an LED array 1701 may include a plurality of LEDs 1707 on acarrier substrate 1705. Carrier substrate 1705 may include variousmaterials, such as GaAs, InP, GaN, AlN, sapphire, SiC, Si, or the like.LEDs 1707 may be fabricated by, for example, growing various epitaxiallayers, forming mesa structures, and forming electrical contacts orelectrodes, before performing the bonding. The epitaxial layers mayinclude various materials, such as GaN, InGaN, (AlGaIn)P, (AlGaIn)AsP,(AlGaIn)AsN, (AlGaIn)Pas, (Eu:InGa)N, (AlGaIn)N, or the like, and mayinclude an n-type layer, a p-type layer, and an active layer thatincludes one or more heterostructures, such as one or more quantum wellsor MQWs. The electrical contacts may include various conductivematerials, such as a metal or a metal alloy.

A wafer 1703 may include a base layer 1709 having passive or activeintegrated circuits (e.g., driver circuits 1711) fabricated thereon.Base layer 1709 may include, for example, a silicon wafer. Drivercircuits 1711 may be used to control the operations of LEDs 1707. Forexample, the driver circuit for each LED 1707 may include a 2T1C pixelstructure that has two transistors and one capacitor. Wafer 1703 mayalso include a bonding layer 1713. Bonding layer 1713 may includevarious materials, such as a metal, an oxide, a dielectric, CuSn, AuTi,and the like. In some embodiments, a patterned layer 1715 may be formedon a surface of bonding layer 1713, where patterned layer 1715 mayinclude a metallic grid made of a conductive material, such as Cu, Ag,Au, Al, or the like.

LED array 1701 may be bonded to wafer 1703 via bonding layer 1713 orpatterned layer 1715. For example, patterned layer 1715 may includemetal pads or bumps made of various materials, such as CuSn, AuSn, ornanoporous Au, that may be used to align LEDs 1707 of LED array 1701with corresponding driver circuits 1711 on wafer 1703. In one example,LED array 1701 may be brought toward wafer 1703 until LEDs 1707 comeinto contact with respective metal pads or bumps corresponding to drivercircuits 1711. Some or all of LEDs 1707 may be aligned with drivercircuits 1711, and may then be bonded to wafer 1703 via patterned layer1715 by various bonding techniques, such as metal-to-metal bonding.After LEDs 1707 have been bonded to wafer 1703, carrier substrate 1705may be removed from LEDs 1707.

FIG. 17B illustrates an example of a method of wafer-to-wafer bondingfor arrays of LEDs according to certain embodiments. As shown in FIG.17B, a first wafer 1702 may include a substrate 1704, a firstsemiconductor layer 1706, active layers 1708, and a second semiconductorlayer 1710. Substrate 1704 may include various materials, such as GaAs,InP, GaN, AlN, sapphire, SiC, Si, or the like. First semiconductor layer1706, active layers 1708, and second semiconductor layer 1710 mayinclude various semiconductor materials, such as GaN, InGaN, (AlGaIn)P,(AlGaIn)AsP, (AlGaIn)AsN, (AlGaIn)Pas, (Eu:InGa)N, (AlGaIn)N, or thelike. In some embodiments, first semiconductor layer 1706 may be ann-type layer, and second semiconductor layer 1710 may be a p-type layer.For example, first semiconductor layer 1706 may be an n-doped GaN layer(e.g., doped with Si or Ge), and second semiconductor layer 1710 may bea p-doped GaN layer (e.g., doped with Mg, Ca, Zn, or Be). Active layers1708 may include, for example, one or more GaN layers, one or more InGaNlayers, one or more AlInGaP layers, and the like, which may form one ormore heterostructures, such as one or more quantum wells or MQWs.

In some embodiments, first wafer 1702 may also include a bonding layer.Bonding layer 1712 may include various materials, such as a metal, anoxide, a dielectric, CuSn, AuTi, or the like. In one example, bondinglayer 1712 may include p-contacts and/or n-contacts (not shown). In someembodiments, other layers may also be included on first wafer 1702, suchas a buffer layer between substrate 1704 and first semiconductor layer1706. The buffer layer may include various materials, such aspolycrystalline GaN or AlN. In some embodiments, a contact layer may bebetween second semiconductor layer 1710 and bonding layer 1712. Thecontact layer may include any suitable material for providing anelectrical contact to second semiconductor layer 1710 and/or firstsemiconductor layer 1706.

First wafer 1702 may be bonded to wafer 1703 that includes drivercircuits 1711 and bonding layer 1713 as described above, via bondinglayer 1713 and/or bonding layer 1712. Bonding layer 1712 and bondinglayer 1713 may be made of the same material or different materials.Bonding layer 1713 and bonding layer 1712 may be substantially flat.First wafer 1702 may be bonded to wafer 1703 by various methods, such asmetal-to-metal bonding, eutectic bonding, metal oxide bonding, anodicbonding, thermo-compression bonding, ultraviolet (UV) bonding, and/orfusion bonding.

As shown in FIG. 17B, first wafer 1702 may be bonded to wafer 1703 withthe p-side (e.g., second semiconductor layer 1710) of first wafer 1702facing down (i.e., toward wafer 1703). After bonding, substrate 1704 maybe removed from first wafer 1702, and first wafer 1702 may then beprocessed from the n-side. The processing may include, for example, theformation of certain mesa shapes for individual LEDs, as well as theformation of optical components corresponding to the individual LEDs.

FIGS. 18A-18D illustrate an example of a method of hybrid bonding forarrays of LEDs according to certain embodiments. The hybrid bonding maygenerally include wafer cleaning and activation, high-precisionalignment of contacts of one wafer with contacts of another wafer,dielectric bonding of dielectric materials at the surfaces of the wafersat room temperature, and metal bonding of the contacts by annealing atelevated temperatures. FIG. 18A shows a substrate 1810 with passive oractive circuits 1820 manufactured thereon. As described above withrespect to FIGS. 17A-17B, substrate 1810 may include, for example, asilicon wafer. Circuits 1820 may include driver circuits for the arraysof LEDs. A bonding layer may include dielectric regions 1840 and contactpads 1830 connected to circuits 1820 through electrical interconnects1822. Contact pads 1830 may include, for example, Cu, Ag, Au, Al, W, Mo,Ni, Ti, Pt, Pd, or the like. Dielectric materials in dielectric regions1840 may include SiCN, SiO₂, SiN, Al₂O₃, HfO₂, ZrO₂, Ta₂O₅, or the like.The bonding layer may be planarized and polished using, for example,chemical mechanical polishing, where the planarization or polishing maycause dishing (a bowl like profile) in the contact pads. The surfaces ofthe bonding layers may be cleaned and activated by, for example, an ion(e.g., plasma) or fast atom (e.g., Ar) beam 1805. The activated surfacemay be atomically clean and may be reactive for formation of directbonds between wafers when they are brought into contact, for example, atroom temperature.

FIG. 18B illustrates a wafer 1850 including an array of micro-LEDs 1870fabricated thereon as described above. Wafer 1850 may be a carrier waferand may include, for example, GaAs, InP, GaN, AlN, sapphire, SiC, Si, orthe like. Micro-LEDs 1870 may include an n-type layer, an active region,and a p-type layer epitaxially grown on wafer 1850. The epitaxial layersmay include various III-V semiconductor materials described above, andmay be processed from the p-type layer side to etch mesa structures inthe epitaxial layers, such as substantially vertical structures,parabolic structures, conic structures, or the like. Passivation layersand/or reflection layers may be formed on the sidewalls of the mesastructures. P-contacts 1880 and n-contacts 1882 may be formed in adielectric material layer 1860 deposited on the mesa structures and maymake electrical contacts with the p-type layer and the n-type layers,respectively. Dielectric materials in dielectric material layer 1860 mayinclude, for example, SiCN, SiO₂, SiN, Al₂O₃, HfO₂, ZrO₂, Ta₂O₅, or thelike. P-contacts 1880 and n-contacts 1882 may include, for example, Cu,Ag, Au, Al, W, Mo, Ni, Ti, Pt, Pd, or the like. The top surfaces ofp-contacts 1880, n-contacts 1882, and dielectric material layer 1860 mayform a bonding layer. The bonding layer may be planarized and polishedusing, for example, chemical mechanical polishing, where the polishingmay cause dishing in p-contacts 1880 and n-contacts 1882. The bondinglayer may then be cleaned and activated by, for example, an ion (e.g.,plasma) or fast atom (e.g., Ar) beam 1815. The activated surface may beatomically clean and reactive for formation of direct bonds betweenwafers when they are brought into contact, for example, at roomtemperature.

FIG. 18C illustrates a room temperature bonding process for bonding thedielectric materials in the bonding layers. For example, after thebonding layer that includes dielectric regions 1840 and contact pads1830 and the bonding layer that includes p-contacts 1880, n-contacts1882, and dielectric material layer 1860 are surface activated, wafer1850 and micro-LEDs 1870 may be turned upside down and brought intocontact with substrate 1810 and the circuits formed thereon. In someembodiments, compression pressure 1825 may be applied to substrate 1810and wafer 1850 such that the bonding layers are pressed against eachother. Due to the surface activation and the dishing in the contacts,dielectric regions 1840 and dielectric material layer 1860 may be indirect contact because of the surface attractive force, and may reactand form chemical bonds between them because the surface atoms may havedangling bonds and may be in unstable energy states after theactivation. Thus, the dielectric materials in dielectric regions 1840and dielectric material layer 1860 may be bonded together with orwithout heat treatment or pressure.

FIG. 18D illustrates an annealing process for bonding the contacts inthe bonding layers after bonding the dielectric materials in the bondinglayers. For example, contact pads 1830 and p-contacts 1880 or n-contacts1882 may be bonded together by annealing at, for example, about 180-400°C. or higher. During the annealing process, heat 1835 may cause thecontacts to expand more than the dielectric materials (due to differentcoefficients of thermal expansion), and thus may close the dishing gapsbetween the contacts such that contact pads 1830 and p-contacts 1880 orn-contacts 1882 may be in contact and may form direct metallic bonds atthe activated surfaces.

In some embodiments where the two bonded wafers include materials havingdifferent coefficients of thermal expansion (CTEs), the dielectricmaterials bonded at room temperature may help to reduce or preventmisalignment of the contact pads caused by the different thermalexpansions. In some embodiments, to further reduce or avoid themisalignment of the contact pads at a high temperature during annealing,trenches may be formed between micro-LEDs, between groups of micro-LEDs,through part or all of the substrate, or the like, before bonding.

After the micro-LEDs are bonded to the driver circuits, the substrate onwhich the micro-LEDs are fabricated may be thinned or removed, andvarious secondary optical components may be fabricated on the lightemitting surfaces of the micro-LEDs to, for example, extract, collimate,and redirect the light emitted from the active regions of themicro-LEDs. In one example, micro-lenses may be formed on themicro-LEDs, where each micro-lens may correspond to a respectivemicro-LED and may help to improve the light extraction efficiency andcollimate the light emitted by the micro-LED. In some embodiments, thesecondary optical components may be fabricated in the substrate or then-type layer of the micro-LEDs. In some embodiments, the secondaryoptical components may be fabricated in a dielectric layer deposited onthe n-type side of the micro-LEDs. Examples of the secondary opticalcomponents may include a lens, a grating, an antireflection (AR)coating, a prism, a photonic crystal, or the like.

FIG. 19 illustrates an example of an LED array 1900 with secondaryoptical components fabricated thereon according to certain embodiments.LED array 1900 may be made by bonding an LED chip or wafer with asilicon wafer including electrical circuits fabricated thereon, usingany suitable bonding techniques described above with respect to, forexample, FIGS. 17A-18D. In the example shown in FIG. 19 , LED array 1900may be bonded using a wafer-to-wafer hybrid bonding technique asdescribed above with respect to FIG. 18A-18D. LED array 1900 may includea substrate 1910, which may be, for example, a silicon wafer. Integratedcircuits 1920, such as LED driver circuits, may be fabricated onsubstrate 1910. Integrated circuits 1920 may be connected to p-contacts1974 and n-contacts 1972 of micro-LEDs 1970 through interconnects 1922and contact pads 1930, where contact pads 1930 may form metallic bondswith p-contacts 1974 and n-contacts 1972. Dielectric layer 1940 onsubstrate 1910 may be bonded to dielectric layer 1960 through fusionbonding.

The substrate (not shown) of the LED chip or wafer may be thinned or maybe removed to expose the n-type layer 1950 of micro-LEDs 1970. Varioussecondary optical components, such as a spherical micro-lens 1982, agrating 1984, a micro-lens 1986, an antireflection layer 1988, and thelike, may be formed in or on top of n-type layer 1950. For example,spherical micro-lens arrays may be etched in the semiconductor materialsof micro-LEDs 1970 using a gray-scale mask and a photoresist with alinear response to exposure light, or using an etch mask formed bythermal reflowing of a patterned photoresist layer. The secondaryoptical components may also be etched in a dielectric layer deposited onn-type layer 1950 using similar photolithographic techniques or othertechniques. For example, micro-lens arrays may be formed in a polymerlayer through thermal reflowing of the polymer layer that is patternedusing a binary mask. The micro-lens arrays in the polymer layer may beused as the secondary optical components or may be used as the etch maskfor transferring the profiles of the micro-lens arrays into a dielectriclayer or a semiconductor layer. The dielectric layer may include, forexample, SiCN, SiO₂, SiN, Al₂O₃, HfO₂, ZrO₂, Ta₂O₅, or the like. In someembodiments, a micro-LED 1970 may have multiple corresponding secondaryoptical components, such as a micro-lens and an anti-reflection coating,a micro-lens etched in the semiconductor material and a micro-lensetched in a dielectric material layer, a micro-lens and a grating, aspherical lens and an aspherical lens, and the like. Three differentsecondary optical components are illustrated in FIG. 19 to show someexamples of secondary optical components that can be formed onmicro-LEDs 1970, which does not necessary imply that different secondaryoptical components are used simultaneously for every LED array.

Embodiments disclosed herein may be used to implement components of anartificial reality system or may be implemented in conjunction with anartificial reality system. Artificial reality is a form of reality thathas been adjusted in some manner before presentation to a user, whichmay include, for example, a virtual reality, an augmented reality, amixed reality, a hybrid reality, or some combination and/or derivativesthereof. Artificial reality content may include completely generatedcontent or generated content combined with captured (e.g., real-world)content. The artificial reality content may include video, audio, hapticfeedback, or some combination thereof, and any of which may be presentedin a single channel or in multiple channels (such as stereo video thatproduces a three-dimensional effect to the viewer). Additionally, insome embodiments, artificial reality may also be associated withapplications, products, accessories, services, or some combinationthereof, that are used to, for example, create content in an artificialreality and/or are otherwise used in (e.g., perform activities in) anartificial reality. The artificial reality system that provides theartificial reality content may be implemented on various platforms,including an HMD connected to a host computer system, a standalone HMD,a mobile device or computing system, or any other hardware platformcapable of providing artificial reality content to one or more viewers.

FIG. 20 is a simplified block diagram of an example electronic system2000 of an example near-eye display (e.g., HMD device) for implementingsome of the examples disclosed herein. Electronic system 2000 may beused as the electronic system of an HMD device or other near-eyedisplays described above. In this example, electronic system 2000 mayinclude one or more processor(s) 2010 and a memory 2020. Processor(s)2010 may be configured to execute instructions for performing operationsat a number of components, and can be, for example, a general-purposeprocessor or microprocessor suitable for implementation within aportable electronic device. Processor(s) 2010 may be communicativelycoupled with a plurality of components within electronic system 2000. Torealize this communicative coupling, processor(s) 2010 may communicatewith the other illustrated components across a bus 2040. Bus 2040 may beany subsystem adapted to transfer data within electronic system 2000.Bus 2040 may include a plurality of computer buses and additionalcircuitry to transfer data.

Memory 2020 may be coupled to processor(s) 2010. In some embodiments,memory 2020 may offer both short-term and long-term storage and may bedivided into several units. Memory 2020 may be volatile, such as staticrandom access memory (SRAM) and/or dynamic random access memory (DRAM)and/or non-volatile, such as read-only memory (ROM), flash memory, andthe like. Furthermore, memory 2020 may include removable storagedevices, such as secure digital (SD) cards. Memory 2020 may providestorage of computer-readable instructions, data structures, programmodules, and other data for electronic system 2000. In some embodiments,memory 2020 may be distributed into different hardware modules. A set ofinstructions and/or code might be stored on memory 2020. Theinstructions might take the form of executable code that may beexecutable by electronic system 2000, and/or might take the form ofsource and/or installable code, which, upon compilation and/orinstallation on electronic system 2000 (e.g., using any of a variety ofgenerally available compilers, installation programs,compression/decompression utilities, etc.), may take the form ofexecutable code.

In some embodiments, memory 2020 may store a plurality of applicationmodules 2022 through 2024, which may include any number of applications.Examples of applications may include gaming applications, conferencingapplications, video playback applications, or other suitableapplications. The applications may include a depth sensing function oreye tracking function. Application modules 2022-2024 may includeparticular instructions to be executed by processor(s) 2010. In someembodiments, certain applications or parts of application modules2022-2024 may be executable by other hardware modules 2080. In certainembodiments, memory 2020 may additionally include secure memory, whichmay include additional security controls to prevent copying or otherunauthorized access to secure information.

In some embodiments, memory 2020 may include an operating system 2025loaded therein. Operating system 2025 may be operable to initiate theexecution of the instructions provided by application modules 2022-2024and/or manage other hardware modules 2080 as well as interfaces with awireless communication subsystem 2030 which may include one or morewireless transceivers. Operating system 2025 may be adapted to performother operations across the components of electronic system 2000including threading, resource management, data storage control and othersimilar functionality.

Wireless communication subsystem 2030 may include, for example, aninfrared communication device, a wireless communication device and/orchipset (such as a Bluetooth® device, an IEEE 802.11 device, a Wi-Fidevice, a WiMax device, cellular communication facilities, etc.), and/orsimilar communication interfaces. Electronic system 2000 may include oneor more antennas 2034 for wireless communication as part of wirelesscommunication subsystem 2030 or as a separate component coupled to anyportion of the system. Depending on desired functionality, wirelesscommunication subsystem 2030 may include separate transceivers tocommunicate with base transceiver stations and other wireless devicesand access points, which may include communicating with different datanetworks and/or network types, such as wireless wide-area networks(WWANs), wireless local area networks (WLANs), or wireless personal areanetworks (WPANs). A WWAN may be, for example, a WiMax (IEEE 802.16)network. A WLAN may be, for example, an IEEE 802.11x network. A WPAN maybe, for example, a Bluetooth network, an IEEE 802.15x, or some othertypes of network. The techniques described herein may also be used forany combination of WWAN, WLAN, and/or WPAN. Wireless communicationssubsystem 2030 may permit data to be exchanged with a network, othercomputer systems, and/or any other devices described herein. Wirelesscommunication subsystem 2030 may include a means for transmitting orreceiving data, such as identifiers of HMD devices, position data, ageographic map, a heat map, photos, or videos, using antenna(s) 2034 andwireless link(s) 2032. Wireless communication subsystem 2030,processor(s) 2010, and memory 2020 may together comprise at least a partof one or more of a means for performing some functions disclosedherein.

Embodiments of electronic system 2000 may also include one or moresensors 2090. Sensor(s) 2090 may include, for example, an image sensor,an accelerometer, a pressure sensor, a temperature sensor, a proximitysensor, a magnetometer, a gyroscope, an inertial sensor (e.g., a modulethat combines an accelerometer and a gyroscope), an ambient lightsensor, or any other similar module operable to provide sensory outputand/or receive sensory input, such as a depth sensor or a positionsensor. For example, in some implementations, sensor(s) 2090 may includeone or more inertial measurement units (IMUs) and/or one or moreposition sensors. An IMU may generate calibration data indicating anestimated position of the HMD device relative to an initial position ofthe HMD device, based on measurement signals received from one or moreof the position sensors. A position sensor may generate one or moremeasurement signals in response to motion of the HMD device. Examples ofthe position sensors may include, but are not limited to, one or moreaccelerometers, one or more gyroscopes, one or more magnetometers,another suitable type of sensor that detects motion, a type of sensorused for error correction of the IMU, or any combination thereof. Theposition sensors may be located external to the IMU, internal to theIMU, or any combination thereof. At least some sensors may use astructured light pattern for sensing.

Electronic system 2000 may include a display module 2060. Display module2060 may be a near-eye display, and may graphically present information,such as images, videos, and various instructions, from electronic system2000 to a user. Such information may be derived from one or moreapplication modules 2022-2024, virtual reality engine 2026, one or moreother hardware modules 2080, a combination thereof, or any othersuitable means for resolving graphical content for the user (e.g., byoperating system 2025). Display module 2060 may use LCD technology, LEDtechnology (including, for example, OLED, ILED, μ-LED, AMOLED, TOLED,etc.), light emitting polymer display (LPD) technology, or some otherdisplay technology.

Electronic system 2000 may include a user input/output module 2070. Userinput/output module 2070 may allow a user to send action requests toelectronic system 2000. An action request may be a request to perform aparticular action. For example, an action request may be to start or endan application or to perform a particular action within the application.User input/output module 2070 may include one or more input devices.Example input devices may include a touchscreen, a touch pad,microphone(s), button(s), dial(s), switch(es), a keyboard, a mouse, agame controller, or any other suitable device for receiving actionrequests and communicating the received action requests to electronicsystem 2000. In some embodiments, user input/output module 2070 mayprovide haptic feedback to the user in accordance with instructionsreceived from electronic system 2000. For example, the haptic feedbackmay be provided when an action request is received or has beenperformed.

Electronic system 2000 may include a camera 2050 that may be used totake photos or videos of a user, for example, for tracking the user'seye position. Camera 2050 may also be used to take photos or videos ofthe environment, for example, for VR, AR, or MR applications. Camera2050 may include, for example, a complementary metal-oxide-semiconductor(CMOS) image sensor with a few millions or tens of millions of pixels.In some implementations, camera 2050 may include two or more camerasthat may be used to capture 3-D images.

In some embodiments, electronic system 2000 may include a plurality ofother hardware modules 2080. Each of other hardware modules 2080 may bea physical module within electronic system 2000. While each of otherhardware modules 2080 may be permanently configured as a structure, someof other hardware modules 2080 may be temporarily configured to performspecific functions or temporarily activated. Examples of other hardwaremodules 2080 may include, for example, an audio output and/or inputmodule (e.g., a microphone or speaker), a near field communication (NFC)module, a rechargeable battery, a battery management system, awired/wireless battery charging system, etc. In some embodiments, one ormore functions of other hardware modules 2080 may be implemented insoftware.

In some embodiments, memory 2020 of electronic system 2000 may alsostore a virtual reality engine 2026. Virtual reality engine 2026 mayexecute applications within electronic system 2000 and receive positioninformation, acceleration information, velocity information, predictedfuture positions, or any combination thereof of the HMD device from thevarious sensors. In some embodiments, the information received byvirtual reality engine 2026 may be used for producing a signal (e.g.,display instructions) to display module 2060. For example, if thereceived information indicates that the user has looked to the left,virtual reality engine 2026 may generate content for the HMD device thatmirrors the user's movement in a virtual environment. Additionally,virtual reality engine 2026 may perform an action within an applicationin response to an action request received from user input/output module2070 and provide feedback to the user. The provided feedback may bevisual, audible, or haptic feedback. In some implementations,processor(s) 2010 may include one or more GPUs that may execute virtualreality engine 2026.

In various implementations, the above-described hardware and modules maybe implemented on a single device or on multiple devices that cancommunicate with one another using wired or wireless connections. Forexample, in some implementations, some components or modules, such asGPUs, virtual reality engine 2026, and applications (e.g., trackingapplication), may be implemented on a console separate from thehead-mounted display device. In some implementations, one console may beconnected to or support more than one HMD.

In alternative configurations, different and/or additional componentsmay be included in electronic system 2000. Similarly, functionality ofone or more of the components can be distributed among the components ina manner different from the manner described above. For example, in someembodiments, electronic system 2000 may be modified to include othersystem environments, such as an AR system environment and/or an MRenvironment.

The methods, systems, and devices discussed above are examples. Variousembodiments may omit, substitute, or add various procedures orcomponents as appropriate. For instance, in alternative configurations,the methods described may be performed in an order different from thatdescribed, and/or various stages may be added, omitted, and/or combined.Also, features described with respect to certain embodiments may becombined in various other embodiments. Different aspects and elements ofthe embodiments may be combined in a similar manner. Also, technologyevolves and, thus, many of the elements are examples that do not limitthe scope of the disclosure to those specific examples.

Specific details are given in the description to provide a thoroughunderstanding of the embodiments. However, embodiments may be practicedwithout these specific details. For example, well-known circuits,processes, systems, structures, and techniques have been shown withoutunnecessary detail in order to avoid obscuring the embodiments. Thisdescription provides example embodiments only, and is not intended tolimit the scope, applicability, or configuration of the invention.Rather, the preceding description of the embodiments will provide thoseskilled in the art with an enabling description for implementing variousembodiments. Various changes may be made in the function and arrangementof elements without departing from the spirit and scope of the presentdisclosure.

Also, some embodiments were described as processes depicted as flowdiagrams or block diagrams. Although each may describe the operations asa sequential process, many of the operations may be performed inparallel or concurrently. In addition, the order of the operations maybe rearranged. A process may have additional steps not included in thefigure. Furthermore, embodiments of the methods may be implemented byhardware, software, firmware, middleware, microcode, hardwaredescription languages, or any combination thereof. When implemented insoftware, firmware, middleware, or microcode, the program code or codesegments to perform the associated tasks may be stored in acomputer-readable medium such as a storage medium. Processors mayperform the associated tasks.

It will be apparent to those skilled in the art that substantialvariations may be made in accordance with specific requirements. Forexample, customized or special-purpose hardware might also be used,and/or particular elements might be implemented in hardware, software(including portable software, such as applets, etc.), or both. Further,connection to other computing devices such as network input/outputdevices may be employed.

With reference to the appended figures, components that can includememory can include non-transitory machine-readable media. The term“machine-readable medium” and “computer-readable medium” may refer toany storage medium that participates in providing data that causes amachine to operate in a specific fashion. In embodiments providedhereinabove, various machine-readable media might be involved inproviding instructions/code to processing units and/or other device(s)for execution. Additionally or alternatively, the machine-readable mediamight be used to store and/or carry such instructions/code. In manyimplementations, a computer-readable medium is a physical and/ortangible storage medium. Such a medium may take many forms, including,but not limited to, non-volatile media, volatile media, and transmissionmedia. Common forms of computer-readable media include, for example,magnetic and/or optical media such as compact disk (CD) or digitalversatile disk (DVD), punch cards, paper tape, any other physical mediumwith patterns of holes, a RAM, a programmable read-only memory (PROM),an erasable programmable read-only memory (EPROM), a FLASH-EPROM, anyother memory chip or cartridge, a carrier wave as described hereinafter,or any other medium from which a computer can read instructions and/orcode. A computer program product may include code and/ormachine-executable instructions that may represent a procedure, afunction, a subprogram, a program, a routine, an application (App), asubroutine, a module, a software package, a class, or any combination ofinstructions, data structures, or program statements.

Those of skill in the art will appreciate that information and signalsused to communicate the messages described herein may be representedusing any of a variety of different technologies and techniques. Forexample, data, instructions, commands, information, signals, bits,symbols, and chips that may be referenced throughout the abovedescription may be represented by voltages, currents, electromagneticwaves, magnetic fields or particles, optical fields or particles, or anycombination thereof.

Terms, “and” and “or” as used herein, may include a variety of meaningsthat are also expected to depend at least in part upon the context inwhich such terms are used. Typically, “or” if used to associate a list,such as A, B, or C, is intended to mean A, B, and C, here used in theinclusive sense, as well as A, B, or C, here used in the exclusivesense. In addition, the term “one or more” as used herein may be used todescribe any feature, structure, or characteristic in the singular ormay be used to describe some combination of features, structures, orcharacteristics. However, it should be noted that this is merely anillustrative example and claimed subject matter is not limited to thisexample. Furthermore, the term “at least one of” if used to associate alist, such as A, B, or C, can be interpreted to mean any combination ofA, B, and/or C, such as A, B, C, AB, AC, BC, AA, ABC, AAB, AABBCCC, etc.

Further, while certain embodiments have been described using aparticular combination of hardware and software, it should be recognizedthat other combinations of hardware and software are also possible.Certain embodiments may be implemented only in hardware, or only insoftware, or using combinations thereof. In one example, software may beimplemented with a computer program product containing computer programcode or instructions executable by one or more processors for performingany or all of the steps, operations, or processes described in thisdisclosure, where the computer program may be stored on a non-transitorycomputer readable medium. The various processes described herein can beimplemented on the same processor or different processors in anycombination.

Where devices, systems, components or modules are described as beingconfigured to perform certain operations or functions, suchconfiguration can be accomplished, for example, by designing electroniccircuits to perform the operation, by programming programmableelectronic circuits (such as microprocessors) to perform the operationsuch as by executing computer instructions or code, or processors orcores programmed to execute code or instructions stored on anon-transitory memory medium, or any combination thereof. Processes cancommunicate using a variety of techniques, including, but not limitedto, conventional techniques for inter-process communications, anddifferent pairs of processes may use different techniques, or the samepair of processes may use different techniques at different times.

The specification and drawings are, accordingly, to be regarded in anillustrative rather than a restrictive sense. It will, however, beevident that additions, subtractions, deletions, and other modificationsand changes may be made thereunto without departing from the broaderspirit and scope as set forth in the claims. Thus, although specificembodiments have been described, these are not intended to be limiting.Various modifications and equivalents are within the scope of thefollowing claims.

What is claimed is:
 1. A micro-light emitting diode (micro-LED) devicecomprising: a substrate including at least a first portion of an n-typesemiconductor layer; and an array of micro-LEDs on the substrate andcharacterized by a pitch equal to or less than 4 μm, each micro-LED ofthe array of micro-LEDs including: a mesa structure including: aplurality of epitaxial layers; and a conductive distributed Braggreflector (DBR) on the plurality of epitaxial layers, the conductive DBRincluding a plurality of transparent conductive oxide layers andcovering at least 80% of a full lateral area of the plurality ofepitaxial layers; a dielectric layer on sidewalls of the mesa structure;a reflective metal layer on sidewalls of the dielectric layer andelectrically coupled to the first portion of the n-type semiconductorlayer; and a first metal electrode in direct contact with the conductiveDBR.
 2. The micro-LED device of claim 1, wherein the conductive DBRaligns with the plurality of epitaxial layers and covers the fulllateral area of the plurality of epitaxial layers in the mesa structure.3. The micro-LED device of claim 1, wherein the plurality of transparentconductive oxide layers includes: a first set of indium tin oxide (ITO)layers characterized by a first refractive index; and a second set ofITO layers characterized by a second refractive index and interleavedwith the first set of ITO layers.
 4. The micro-LED device of claim 3,wherein: the first set of ITO layers includes crystalline ITO; and thesecond set of ITO layers includes porous ITO.
 5. The micro-LED device ofclaim 3, wherein: the first set of ITO layers includes ITO nanorods in afirst orientation; and the second set of ITO layers includes ITOnanorods in a second orientation that is different from the firstorientation.
 6. The micro-LED device of claim 3, wherein: the firstrefractive index is greater than 2.0 for a target wavelength; and thesecond refractive index is less than 1.7 for the target wavelength. 7.The micro-LED device of claim 1, wherein a reflectance of the conductiveDBR for a target wavelength is greater than 90%.
 8. The micro-LED deviceof claim 1, wherein the plurality of epitaxial layers includes: a secondportion of the n-type semiconductor layer; an active region includingone or more quantum wells configured to emit visible light; and a p-typesemiconductor layer coupled to the conductive DBR.
 9. The micro-LEDdevice of claim 1, wherein each micro-LED of the array of micro-LEDsfurther includes a micro-lens on the substrate.
 10. The micro-LED deviceof claim 1, further comprising at least one of: a second metal electrodeelectrically coupled to the reflective metal layer and the first portionof the n-type semiconductor layer; or a transparent conductive oxidelayer electrically coupled to the first portion of the n-typesemiconductor layer or the reflective metal layer.
 11. A micro-lightemitting diode (micro-LED) comprising: a substrate including at least afirst portion of an n-type semiconductor layer; a mesa structure on thesubstrate and characterized by a linear lateral dimension equal to orless than 3 μm, the mesa structure including: a plurality of epitaxiallayers; and a conductive distributed Bragg reflector (DBR) on theplurality of epitaxial layers, the conductive DBR including a pluralityof transparent conductive oxide layers and covering at least 80% of afull lateral area of the plurality of epitaxial layers; a dielectriclayer on sidewalls of the mesa structure; a reflective metal layer onsidewalls of the dielectric layer and electrically coupled to the firstportion of the n-type semiconductor layer; and a first metal electrodein direct contact with the conductive DBR.
 12. The micro-LED of claim11, wherein the conductive DBR aligns with the plurality of epitaxiallayers and covers the full lateral area of the plurality of epitaxiallayers in the mesa structure.
 13. The micro-LED of claim 11, wherein theplurality of transparent conductive oxide layers includes: a first setof indium tin oxide (ITO) layers characterized by a first refractiveindex; and a second set of ITO layers characterized by a secondrefractive index and interleaved with the first set of ITO layers,wherein the first set of ITO layers and the second set of ITO layershave different porosities or different nanorod orientations.
 14. Themicro-LED of claim 11, wherein a reflectance of the conductive DBR for atarget wavelength is greater than 90%.